s_cbranch_join GPU Native ISA AMD Scalar

Scalar Arithmetic

s_cbranch_join

Conditional branch join point (end of conditional branch block).

Encoding

Binary Layout (AMD CDNA 4)
101111101
31:23
SDST
22:16
00101110
15:8
SSRC0
7:0
 

The ENC_SOP1 layout from AMD's machine-readable ISA specification (AMD CDNA 4). Opcode 46 in OP rebuilds 0xBE802E00, an identifier AMD lists for this encoding. The same in the other 3 generations that define it.

Format SOP1
Width 32 bits
Opcode 46
Identifier 0xBE802E00

Operands

  • SSRC0
    Read. N/A Data format: N/A (OPR_SREG, FMT_NUM_B32)

In AMD's order, as its machine-readable ISA specification lists them for the ENC_SOP1 encoding (AMD CDNA 4).

GFX Target Compatibility

Per-target GFX compatibility has not yet been verified for this instruction.

Related

More in Scalar Arithmetic

Reference

AMDGPU / GFX ISA

Description

Conditional branch join point (end of conditional branch block). S0 is saved CSP value. See S_CBRANCH_G_FORK and S_CBRANCH_I_FORK for related instructions.

Semantics

saved_csp = S0.u32; if WAVE_MODE.CSP.u32 == saved_csp then PC += 4LL; // Second time to JOIN: continue with program. else WAVE_MODE.CSP -= 3'1U; // First time to JOIN; jump to other FORK path. { PC, EXEC } = SGPR[WAVE_MODE.CSP.u32 * 4U].b128; // Read 128 bits from 4 consecutive SGPRs. endif

Example

s_cbranch_join s1

A real instruction accepted by the LLVM assembler, taken verbatim from LLVM's own AMDGPU MC test suite (gfx7_asm_sop1.s). Not from an AMD document, and not authored here.

Sources