s_cbranch_i_fork GPU Native ISA AMD Scalar

Scalar Arithmetic

s_cbranch_i_fork

Conditional branch using branch-stack.

Encoding

Binary Layout (AMD CDNA 4)
1011
31:28
10000
27:23
SDST
22:16
SIMM16
15:0
 

The ENC_SOPK layout from AMD's machine-readable ISA specification (AMD CDNA 4). Opcode 16 in OP rebuilds 0xB8000000, an identifier AMD lists for this encoding. The same in the other 3 generations that define it.

Format SOPK
Width 32 bits
Opcode 16
Identifier 0xB8000000

Operands

  • SDST
    Read. N/A Data format: N/A (OPR_SDST, FMT_NUM_B64)
  • SIMM16
    Read. A relative jump offset. Data format: N/A (OPR_LABEL, FMT_NUM_I16)

In AMD's order, as its machine-readable ISA specification lists them for the ENC_SOPK encoding (AMD CDNA 4).

GFX Target Compatibility

Per-target GFX compatibility has not yet been verified for this instruction.

Related

More in Scalar Arithmetic

Reference

AMDGPU / GFX ISA

Example

s_cbranch_i_fork vcc, 12609

A real instruction accepted by the LLVM assembler, taken verbatim from LLVM's own AMDGPU MC test suite (gfx7_asm_sopk.s). Not from an AMD document, and not authored here.

Sources