s_bitset0_b32 GPU Native ISA AMD Scalar
S BITSET0 B32 Scalar Arithmetic
s_bitset0_b32
Given a bit offset in a scalar input, set the indicated bit in the destination scalar register to 0.
Encoding
Verified bit-level encoding data is not yet available for this instruction.
The instruction-format classification below (SOP1)
is well-documented and stable; exact per-target opcode/field bit positions have not
yet been imported from a verified source.
Operands
Operand details have not yet been curated for this instruction.
GFX Target Compatibility
| Target | Support |
|---|---|
| gfx1100 | ✅ Supported |
Related
More in Scalar Arithmetic
Reference
AMDGPU / GFX ISA
Semantics
D0.u32[S0.u32[4 : 0]] = 1'0U
Example
s_bitset0_b32 s0, 0A real instruction accepted by the LLVM assembler, taken verbatim from LLVM's own AMDGPU MC test suite (gfx11). Not from an AMD document, and not authored here.
Sources
- User Guide for AMDGPU Backend ↗ - LLVM Project
-
"AMD Instinct MI300" Instruction Set Architecture: Reference Guide ↗
- Advanced Micro Devices, Inc.
Reference Guide, page 122. - LLVM MC assembler tests for AMDGPU (gfx11) ↗ - LLVM Project