s_and_not0_wrexec_b32 GPU Native ISA AMD Scalar

Scalar Arithmetic

s_and_not0_wrexec_b32

Calculate bitwise AND on the EXEC mask and the negation of the scalar input, store the calculated result into the EXEC mask and also into the scalar…

Also written as s_andn1_wrexec_b32. AMD's machine-readable ISA specification lists this name for the same instruction.

Encoding

Binary Layout (AMD CDNA 5)
101111101
31:23
SDST
22:16
00110100
15:8
SSRC0
7:0
 

The ENC_SOP1 layout from AMD's machine-readable ISA specification (AMD CDNA 5). Opcode 52 in OP rebuilds 0xBE803400, an identifier AMD lists for this encoding. The same in the other 3 generations that define it.

Format SOP1
Width 32 bits
Opcode 52
Identifier 0xBE803400

Operands

  • SDST
    Written. Any scalar GPR operand including VCC and NULL. Data format: Unsigned 32-bit integral data. (OPR_SREG, FMT_NUM_U32)
  • SSRC0
    Read. All scalar operands. Covers all operands that are allowed as scalar sources. Data format: Unsigned 32-bit integral data. (OPR_SSRC, FMT_NUM_U32)

In AMD's order, as its machine-readable ISA specification lists them for the ENC_SOP1 encoding (AMD CDNA 5).

GFX Target Compatibility

TargetSupport
gfx1100✅ Supported

Related

More in Scalar Arithmetic

Reference

AMDGPU / GFX ISA

Description

Calculate bitwise AND on the EXEC mask and the negation of the scalar input, store the calculated result into the EXEC mask and also into the scalar destination register, and set SCC iff the calculated result is nonzero.

Example

s_and_not0_wrexec_b32 s5, s1

A real instruction accepted by the LLVM assembler, taken verbatim from LLVM's own AMDGPU MC test suite. Not from an AMD document, and not authored here.

Sources