s_add_i32 GPU Native ISA AMD Scalar
S ADD I32 Scalar Arithmetic
s_add_i32
Add two signed 32-bit integer inputs, store the result into a scalar register and store the carry-out bit into SCC.
Encoding
Verified bit-level encoding data is not yet available for this instruction.
The instruction-format classification below (SOP2)
is well-documented and stable; exact per-target opcode/field bit positions have not
yet been imported from a verified source.
Operands
Operand details have not yet been curated for this instruction.
GFX Target Compatibility
| Target | Support |
|---|---|
| gfx1100 | ✅ Supported |
This opcode is not suitable for use with S_ADDC_U32 for implementing 64-bit operations.
Related
More in Scalar Arithmetic
Reference
AMDGPU / GFX ISA
Semantics
tmp = S0.i32 + S1.i32;
SCC = ((S0.u32[31] == S1.u32[31]) && (S0.u32[31] != tmp.u32[31]));
// signed overflow.
D0.i32 = tmp.i32
Example
s_add_i32 s0, 0, s2A real instruction accepted by the LLVM assembler, taken verbatim from LLVM's own AMDGPU MC test suite (gfx11). Not from an AMD document, and not authored here.
Sources
- User Guide for AMDGPU Backend ↗ - LLVM Project
-
"AMD Instinct MI300" Instruction Set Architecture: Reference Guide ↗
- Advanced Micro Devices, Inc.
Reference Guide, page 97. - LLVM MC assembler tests for AMDGPU (gfx11) ↗ - LLVM Project