Bit Reverse Bit Manipulation
Reverse the order of bits in an operand.
Vendor-Neutral Definition
d[i] = a[width-1-i] for every bit position i.
⚠️ Cross-vendor mappings describe semantic relationships and are not guaranteed one-to-one compiler
translations.
equivalent with restrictions
Both reverse the bit order of a 32-bit operand; AMDGPU splits scalar and vector forms where PTX has one generic brev.
| Property | NVIDIA PTX | AMDGPU |
|---|---|---|
| Instruction | brev | v_bfrev_b32, s_brev_b32 |
| ISA Layer | Virtual | Native |
| Data Types | - | b32 |
| Version / Target Introduced | PTX ISA 2.0 | gfx1100, gfx1100 |
Important Differences
- PTX's brev also has a .b64 form; AMDGPU's bit-reverse instructions in this dataset are 32-bit only (b32) - a 64-bit reverse requires reversing each 32-bit half and swapping them.
Source Evidence
- Parallel Thread Execution ISA ↗ - NVIDIA Corporation
- User Guide for AMDGPU Backend ↗ - LLVM Project
Verification method: documentation