ds_add_u32 GPU Native ISA AMD Vector

DS ADD U32 Atomics

ds_add_u32 ADDR, DATA, offset

Atomically add a per-lane value to an LDS location.

Encoding

Verified bit-level encoding data is not yet available for this instruction. The instruction-format classification below (DS) is well-documented and stable; exact per-target opcode/field bit positions have not yet been imported from a verified source.
Format DS
Width 32 bits
Execution Unit LDS Unit
Register Classes VGPR
Memory Segment LDS/shared

Operands

  • ADDR
    Per-lane LDS byte address
  • DATA
    Per-lane value to add
  • offset
    Immediate byte offset

GFX Target Compatibility

TargetSupport
gfx942✅ Supported
gfx1100✅ Supported

Related PTX Concepts

Atomic Add ↗
equivalent with restrictions
atom (PTX)

Related

More in Atomics

Reference

AMDGPU / GFX ISA

Description

Add two unsigned 32-bit integer values stored in the data register and a location in a data share.

Semantics

old = LDS[ADDR[lane] + offset]; LDS[...] = old + DATA[lane]; indivisible with respect to other lanes/waves in the workgroup.

Example

ds_add_u32  v0, v1   // LDS[v0] += v1

Original illustrative example, written for this site (not reproduced from a specific AMD document).

Sources