ds_add_u32 GPU Native ISA AMD Vector

Atomics

ds_add_u32 ADDR, DATA, offset

Atomically add a per-lane value to an LDS location.

Encoding

Binary Layout (AMD CDNA 5)
VDST
63:56
DATA1
55:48
DATA0
47:40
ADDR
39:32
110110
31:26
00000000
25:18
unassigned
17:16
OFFSET1
15:8
OFFSET0
7:0
 

The ENC_VDS layout from AMD's machine-readable ISA specification (AMD CDNA 5). Opcode 0 in OP rebuilds 0x00000000D8000000, an identifier AMD lists for this encoding. Bits marked unassigned have no field in the specification. Not the same in every generation: AMD CDNA 4 (encoding ENC_DS, field layout), AMD CDNA 3 (encoding ENC_DS, field layout), AMD CDNA 2 (encoding ENC_DS, field layout), AMD CDNA 1 (encoding ENC_DS, field layout), AMD RDNA 3.5 (encoding ENC_DS, field layout), AMD RDNA 3 (encoding ENC_DS, field layout), AMD RDNA 2 (encoding ENC_DS, field layout), AMD RDNA 1 (encoding ENC_DS, field layout). The same in AMD RDNA 4.

Format DS
Width 64 bits
Opcode 0
Identifier 0x00000000D8000000
Execution Unit LDS Unit
Register Classes VGPR
Memory Segment LDS/shared

Operands

  • ADDR
    Per-lane LDS byte address
  • DATA
    Per-lane value to add
  • offset
    Immediate byte offset

GFX Target Compatibility

TargetSupport
gfx942✅ Supported
gfx1100✅ Supported

Related PTX Concepts

Atomic Add ↗
equivalent with restrictions
atom (PTX)

Related

More in Atomics

Reference

AMDGPU / GFX ISA

Description

Add two unsigned 32-bit integer values stored in the data register and a location in a data share.

Semantics

old = LDS[ADDR[lane] + offset]; LDS[...] = old + DATA[lane]; indivisible with respect to other lanes/waves in the workgroup.

Example

ds_add_u32  v0, v1   // LDS[v0] += v1

Original illustrative example, written for this site (not reproduced from a specific AMD document).

Sources