global_atomic_add GPU Native ISA AMD Vector

GLOBAL ATOMIC ADD Atomics

global_atomic_add VDST, VADDR, VDATA, SADDR

Atomically add a per-lane value to a global-memory location.

Encoding

Verified bit-level encoding data is not yet available for this instruction. The instruction-format classification below (GLOBAL) is well-documented and stable; exact per-target opcode/field bit positions have not yet been imported from a verified source.
Format GLOBAL
Width 32 bits
Execution Unit Vector Memory Unit
Register Classes VGPR, SGPR
Memory Segment global

Operands

  • VDST
    Optional destination VGPR (previous value)
  • VADDR
    Per-lane 64-bit address
  • VDATA
    Per-lane value to add
  • SADDR
    Optional uniform base

GFX Target Compatibility

TargetSupport
gfx942✅ Supported
gfx1100✅ Supported

Related PTX Concepts

Atomic Add ↗
equivalent with restrictions
atom (PTX)

Related

More in Atomics

Reference

AMDGPU / GFX ISA

Description

Add two unsigned 32-bit integer values stored in the data register and a location in the global aperture. Store the original value from global aperture into a vector register iff the SC0 bit is set.

Semantics

old = *(VADDR[lane] + SADDR + offset); *(...) = old + VDATA[lane]; indivisible with respect to other lanes/waves targeting the same address. VDST optionally receives old.

Example

global_atomic_add  v2, v[0:1], v2, off   // *(v[0:1]) += v2 per lane, v2 <- old value

Original illustrative example, written for this site (not reproduced from a specific AMD document).

Sources