Atomic Bitwise Operations Atomics

Apply AND, OR or XOR to a memory location indivisibly.

Vendor-Neutral Definition

*addr = *addr op val for op in {and, or, xor}, performed atomically. The common use is setting or clearing flag bits shared between threads.
⚠️ Cross-vendor mappings describe semantic relationships and are not guaranteed one-to-one compiler translations.
equivalent with restrictions Direct correspondence for all three operations, differing only in how the address space and the return value are selected.
Property NVIDIA PTX AMDGPU
Instruction atom global_atomic_and, global_atomic_or, global_atomic_xor
ISA Layer Virtual Native
Data Types b32, b64, f32, f64, s32, u32, u64 -
Version / Target Introduced PTX ISA 1.1 -

Important Differences

  • As with the other atomics, AMDGPU encodes the address space in the opcode (global_ against ds_) while PTX uses a modifier on atom.
  • Where the old value is not needed, PTX red.and is cheaper than atom.and, and AMDGPU's non-_rtn form is cheaper than the _rtn form, for the same reason: no result register and no wait.

Source Evidence

Verification method: documentation