Vector Arithmetic Instructions
558 AMDGPU instructions in this category - showing 58 per page, page 6 of 6 - click any row for encoding, pseudocode, and full documentation.
| Mnemonic | Syntax | Format | Summary |
|---|---|---|---|
| v_rsq_bf16 | v_rsq_bf16 | VOP1 | AMDGPU VOP1 vector instruction. (Format and name extracted from LLVM's AMDGPU backend source - semantics not yet curated.) |
| v_rsq_f16 | v_rsq_f16 | VOP1 | Calculate the reciprocal of the square root of the half-precision float input using IEEE rules and store the result into a vector register. |
| v_rsq_f32 | v_rsq_f32 VDST, S0 | VOP1 | Per-lane fast approximate reciprocal square root. |
| v_rsq_f64 | v_rsq_f64 | VOP1 | Calculate the reciprocal of the square root of the double-precision float input using IEEE rules and store the result into a vector register. |
| v_sad_hi_u8 | v_sad_hi_u8 | VOP3 | Calculate the sum of absolute differences of elements in two packed 4-component unsigned 8-bit integer inputs, shift the sum left by 16 bits, add an… |
| v_sad_u16 | v_sad_u16 | VOP3 | Calculate the sum of absolute differences of elements in two packed 2-component unsigned 16-bit integer inputs, add an unsigned 32-bit integer value… |
| v_sad_u32 | v_sad_u32 | VOP3 | Calculate the absolute difference of two unsigned 32-bit integer inputs, add an unsigned 32-bit integer value from the third input and store the… |
| v_sad_u8 | v_sad_u8 | VOP3 | Calculate the sum of absolute differences of elements in two packed 4-component unsigned 8-bit integer inputs, add an unsigned 32-bit integer value… |
| v_sat_pk4_i4_i8 | v_sat_pk4_i4_i8 | VOP1 | AMDGPU VOP1 vector instruction operating on i8 data. (Format and name extracted from LLVM's AMDGPU backend source - semantics not yet curated.) |
| v_sat_pk4_u4_u8 | v_sat_pk4_u4_u8 | VOP1 | AMDGPU VOP1 vector instruction operating on u8 data. (Format and name extracted from LLVM's AMDGPU backend source - semantics not yet curated.) |
| v_sat_pk_u8_i16 | v_sat_pk_u8_i16 | VOP1 | Given 2 signed 16-bit integer inputs, saturate each input over an unsigned 8-bit integer range, pack the resulting values into a packed 16-bit value… |
| v_screen_partition_4se_b32 | v_screen_partition_4se_b32 | VOP1 | 4SE version of LUT instruction for screen partitioning/filtering. |
| v_sin_bf16 | v_sin_bf16 | VOP1 | AMDGPU VOP1 vector instruction. (Format and name extracted from LLVM's AMDGPU backend source - semantics not yet curated.) |
| v_sin_f16 | v_sin_f16 | VOP1 | Calculate the trigonometric sine of a half-precision float value using IEEE rules and store the result into a vector register. |
| v_sin_f32 | v_sin_f32 VDST, S0 | VOP1 | Per-lane fast approximate sine. |
| v_sqrt_bf16 | v_sqrt_bf16 | VOP1 | AMDGPU VOP1 vector instruction. (Format and name extracted from LLVM's AMDGPU backend source - semantics not yet curated.) |
| v_sqrt_f16 | v_sqrt_f16 | VOP1 | Calculate the square root of the half-precision float input using IEEE rules and store the result into a vector register. |
| v_sqrt_f32 | v_sqrt_f32 | VOP1 | Calculate the square root of the single-precision float input using IEEE rules and store the result into a vector register. |
| v_sqrt_f64 | v_sqrt_f64 | VOP1 | Calculate the square root of the double-precision float input using IEEE rules and store the result into a vector register. |
| v_sub_co_u32 | v_sub_co_u32 | VOP2 | Subtract the second unsigned 32-bit integer input from the first input, store the result into a vector register and store the carry-out mask into a… |
| v_sub_f16 | v_sub_f16 | VOP2 | Subtract the second floating point input from the first input and store the result into a vector register. |
| v_sub_f32 | v_sub_f32 VDST, S0, S1 | VOP2 | Per-lane single-precision floating-point subtract. |
| v_sub_i16 | v_sub_i16 | VOP3 | Subtract the second signed 16-bit integer input from the first input and store the result into a vector register. No carry-in or carry-out support. |
| v_sub_i32 | v_sub_i32 | VOP2 | Subtract the second signed 32-bit integer input from the first input and store the result into a vector register. No carry-in or carry-out support. |
| v_sub_nc_i16 | v_sub_nc_i16 | VOP3 | Subtract the second signed 16-bit integer input from the first input and store the result into a vector register. No carry-in or carry-out support. |
| v_sub_nc_i32 | v_sub_nc_i32 | VOP3 | Subtract the second signed 32-bit integer input from the first input and store the result into a vector register. No carry-in or carry-out support. |
| v_sub_nc_u16 | v_sub_nc_u16 | VOP3 | Subtract the second unsigned 16-bit integer input from the first input and store the result into a vector register. No carry-in or carry-out support. |
| v_sub_nc_u64 | v_sub_nc_u64 | VOP2 | AMDGPU VOP2 vector instruction operating on u64 data. (Format and name extracted from LLVM's AMDGPU backend source - semantics not yet curated.) |
| v_sub_u16 | v_sub_u16 | VOP2 | Subtract the second unsigned 16-bit integer input from the first input and store the result into a vector register. No carry-in or carry-out support. |
| v_sub_u32 | v_sub_u32 | VOP2 | Subtract the second unsigned 32-bit integer input from the first input and store the result into a vector register. No carry-in or carry-out support. |
| v_subb_co_u32 | v_subb_co_u32 | VOP2 | Subtract the second unsigned 32-bit integer input from the first input, subtract a bit from the carry-in mask, store the result into a vector… |
| v_subb_u32 | v_subb_u32 | VOP2 | AMDGPU VOP2 vector instruction operating on u32 data. (Format and name extracted from LLVM's AMDGPU backend source - semantics not yet curated.) |
| v_subbrev_co_u32 | v_subbrev_co_u32 | VOP2 | Subtract the first unsigned 32-bit integer input from the second input, subtract a bit from the carry-in mask, store the result into a vector… |
| v_subbrev_u32 | v_subbrev_u32 | VOP2 | AMDGPU VOP2 vector instruction operating on u32 data. (Format and name extracted from LLVM's AMDGPU backend source - semantics not yet curated.) |
| v_subrev_co_u32 | v_subrev_co_u32 | VOP2 | Subtract the first unsigned 32-bit integer input from the second input, store the result into a vector register and store the carry-out mask into a… |
| v_subrev_f16 | v_subrev_f16 | VOP2 | Subtract the first floating point input from the second input and store the result into a vector register. |
| v_subrev_f32 | v_subrev_f32 | VOP2 | Subtract the first floating point input from the second input and store the result into a vector register. |
| v_subrev_i32 | v_subrev_i32 | VOP2 | AMDGPU VOP2 vector instruction operating on i32 data. (Format and name extracted from LLVM's AMDGPU backend source - semantics not yet curated.) |
| v_subrev_u16 | v_subrev_u16 | VOP2 | Subtract the first unsigned 16-bit integer input from the second input and store the result into a vector register. No carry-in or carry-out support. |
| v_subrev_u32 | v_subrev_u32 | VOP2 | Subtract the first unsigned 32-bit integer input from the second input and store the result into a vector register. No carry-in or carry-out support. |
| v_swap_b16 | v_swap_b16 | VOP1 | Swap the values in two vector registers. |
| v_swap_b32 | v_swap_b32 | VOP1 | Swap the values in two vector registers. |
| v_swaprel_b32 | v_swaprel_b32 | VOP1 | Swap the values in two relatively-indexed vector registers. |
| v_tanh_bf16 | v_tanh_bf16 | VOP1 | AMDGPU VOP1 vector instruction. (Format and name extracted from LLVM's AMDGPU backend source - semantics not yet curated.) |
| v_tanh_f16 | v_tanh_f16 | VOP1 | AMDGPU VOP1 vector instruction operating on f16 data. (Format and name extracted from LLVM's AMDGPU backend source - semantics not yet curated.) |
| v_tanh_f32 | v_tanh_f32 | VOP1 | AMDGPU VOP1 vector instruction operating on f32 data. (Format and name extracted from LLVM's AMDGPU backend source - semantics not yet curated.) |
| v_trig_preop_f64 | v_trig_preop_f64 | VOP3 | Look up a 53-bit segment of 2/PI using an integer segment select in the second input. |
| v_trunc_f16 | v_trunc_f16 | VOP1 | Compute the integer part of a half-precision float input using round toward zero semantics and store the result in floating point format into a… |
| v_trunc_f32 | v_trunc_f32 | VOP1 | Compute the integer part of a single-precision float input using round toward zero semantics and store the result in floating point format into a… |
| v_trunc_f64 | v_trunc_f64 | VOP1 | Compute the integer part of a double-precision float input using round toward zero semantics and store the result in floating point format into a… |
| v_writelane_b32 | v_writelane_b32 | VOP2 | Write the scalar value in the first input into the specified lane of a vector register where the lane select is in the second input. |
| v_xad_u32 | v_xad_u32 | VOP3 | Calculate bitwise XOR of the first two vector inputs, then add the third vector input to the intermediate result, then store the final result into a… |
| v_xnor_b32 | v_xnor_b32 | VOP2 | Calculate bitwise XNOR on two vector inputs and store the result into a vector register. |
| v_xor3_b32 | v_xor3_b32 | VOP3 | Calculate the bitwise XOR of three vector inputs and store the result into a vector register. |
| v_xor_b16 | v_xor_b16 | VOP3 | Calculate bitwise XOR on two vector inputs and store the result into a vector register. |
| v_xor_b16_fake16 | v_xor_b16_fake16 | VOP2 | AMDGPU VOP2 vector instruction operating on b16 data. (Format and name extracted from LLVM's AMDGPU backend source - semantics not yet curated.) |
| v_xor_b16_t16 | v_xor_b16_t16 | VOP2 | AMDGPU VOP2 vector instruction operating on b16 data. (Format and name extracted from LLVM's AMDGPU backend source - semantics not yet curated.) |
| v_xor_b32 | v_xor_b32 | VOP2 | Calculate bitwise XOR on two vector inputs and store the result into a vector register. |