Vector Arithmetic Instructions
597 AMDGPU instructions in this category - showing 97 per page, page 6 of 6 - click any row for encoding, pseudocode, and full documentation.
| Mnemonic | Syntax | Format | Summary |
|---|---|---|---|
| v_or3_b32 | v_or3_b32 | VOP3 | Calculate the bitwise OR of three vector inputs and store the result into a vector register. |
| v_or_b16 | v_or_b16 | VOP3 | Calculate bitwise OR on two vector inputs and store the result into a vector register. |
| v_or_b16_fake16 | v_or_b16_fake16 | VOP2 | AMDGPU VOP2 vector instruction operating on b16 data. (Format and name extracted from LLVM's AMDGPU backend source - semantics not yet curated.) |
| v_or_b16_t16 | v_or_b16_t16 | VOP2 | AMDGPU VOP2 vector instruction operating on b16 data. (Format and name extracted from LLVM's AMDGPU backend source - semantics not yet curated.) |
| v_or_b32 | v_or_b32 | VOP2 | Calculate bitwise OR on two vector inputs and store the result into a vector register. |
| v_pack_b32_f16 | v_pack_b32_f16 | VOP3 | Pack two half-precision float values into a single 32-bit value and store the result into a vector register. |
| v_perm_b32 | v_perm_b32 | VOP3 | Permute a 64-bit value constructed from two vector inputs (most significant bits come from the first input) using a per-lane selector from the third… |
| v_perm_pk16_b4_u4 | v_perm_pk16_b4_u4 | VOP3 | AMDGPU VOP3 vector instruction. (Format and name extracted from LLVM's AMDGPU backend source - semantics not yet curated.) |
| v_perm_pk16_b6_u4 | v_perm_pk16_b6_u4 | VOP3 | AMDGPU VOP3 vector instruction. (Format and name extracted from LLVM's AMDGPU backend source - semantics not yet curated.) |
| v_perm_pk16_b8_u4 | v_perm_pk16_b8_u4 | VOP3 | AMDGPU VOP3 vector instruction operating on b8 data. (Format and name extracted from LLVM's AMDGPU backend source - semantics not yet curated.) |
| v_permlane16_b32 | v_permlane16_b32 | VOP3 | Perform arbitrary gather-style operation within a row (16 contiguous lanes). |
| v_permlane16_swap_b32 | v_permlane16_swap_b32 | VOP1 | Swap data between two vector registers. Odd rows of the first operand are swapped with even rows of the second operand (one row is 16 lanes). |
| v_permlane16_var_b32 | v_permlane16_var_b32 | VOP3 | Perform arbitrary gather-style operation within a row (16 contiguous lanes). |
| v_permlane32_swap_b32 | v_permlane32_swap_b32 | VOP1 | Swap data between two vector registers. Rows 2 and 3 of the first operand are swapped with rows 0 and 1 of the second operand (one row is 16 lanes). |
| v_permlane64_b32 | v_permlane64_b32 | VOP1 | Perform a specific permutation across lanes where the high half and low half of a wave64 are swapped. Performs no operation in wave32 mode. |
| v_permlane_bcast_b32 | v_permlane_bcast_b32 | VOP3 | AMDGPU VOP3 vector instruction operating on b32 data. (Format and name extracted from LLVM's AMDGPU backend source - semantics not yet curated.) |
| v_permlane_down_b32 | v_permlane_down_b32 | VOP3 | AMDGPU VOP3 vector instruction operating on b32 data. (Format and name extracted from LLVM's AMDGPU backend source - semantics not yet curated.) |
| v_permlane_idx_gen_b32 | v_permlane_idx_gen_b32 | VOP3 | AMDGPU VOP3 vector instruction operating on b32 data. (Format and name extracted from LLVM's AMDGPU backend source - semantics not yet curated.) |
| v_permlane_up_b32 | v_permlane_up_b32 | VOP3 | AMDGPU VOP3 vector instruction operating on b32 data. (Format and name extracted from LLVM's AMDGPU backend source - semantics not yet curated.) |
| v_permlane_xor_b32 | v_permlane_xor_b32 | VOP3 | AMDGPU VOP3 vector instruction operating on b32 data. (Format and name extracted from LLVM's AMDGPU backend source - semantics not yet curated.) |
| v_permlanex16_b32 | v_permlanex16_b32 | VOP3 | Perform arbitrary gather-style operation across two rows (each row is 16 contiguous lanes). |
| v_permlanex16_var_b32 | v_permlanex16_var_b32 | VOP3 | Perform arbitrary gather-style operation across two rows (each row is 16 contiguous lanes). |
| v_pipeflush | v_pipeflush | VOP1 | Flush the vector ALU pipeline through the destination cache. |
| v_pk_fmac_f16 | v_pk_fmac_f16 | VOP2 | Multiply two packed half-precision float inputs component-wise and accumulate the result into the destination register using fused multiply add. |
| v_prng_b32 | v_prng_b32 | VOP1 | Generate a pseudorandom number using an LFSR (linear feedback shift register) seeded with the vector input, then store the result into a vector… |
| v_qsad_pk_u16_u8 | v_qsad_pk_u16_u8 | VOP3 | Perform the V_SAD_U8 operation four times using different slices of the first array, all entries of the second array and each entry of the third… |
| v_rcp_bf16 | v_rcp_bf16 | VOP1 | AMDGPU VOP1 vector instruction. (Format and name extracted from LLVM's AMDGPU backend source - semantics not yet curated.) |
| v_rcp_f16 | v_rcp_f16 | VOP1 | Calculate the reciprocal of the half-precision float input using IEEE rules and store the result into a vector register. |
| v_rcp_f32 | v_rcp_f32 | VOP1 | Calculate the reciprocal of the single-precision float input using IEEE rules and store the result into a vector register. |
| v_rcp_f64 | v_rcp_f64 | VOP1 | Calculate the reciprocal of the double-precision float input using IEEE rules and store the result into a vector register. |
| v_rcp_iflag_f32 | v_rcp_iflag_f32 | VOP1 | Calculate the reciprocal of the vector float input in a manner suitable for integer division and store the result into a vector register. |
| v_readlane_b32 | v_readlane_b32 | VOP2 | Read the scalar value in the specified lane of the first input where the lane select is in the second input. Store the result into a scalar register. |
| v_rndne_f16 | v_rndne_f16 | VOP1 | Round the half-precision float input to the nearest even integer and store the result in floating point format into a vector register. |
| v_rndne_f32 | v_rndne_f32 | VOP1 | Round the single-precision float input to the nearest even integer and store the result in floating point format into a vector register. |
| v_rndne_f64 | v_rndne_f64 | VOP1 | Round the double-precision float input to the nearest even integer and store the result in floating point format into a vector register. |
| v_rsq_bf16 | v_rsq_bf16 | VOP1 | AMDGPU VOP1 vector instruction. (Format and name extracted from LLVM's AMDGPU backend source - semantics not yet curated.) |
| v_rsq_f16 | v_rsq_f16 | VOP1 | Calculate the reciprocal of the square root of the half-precision float input using IEEE rules and store the result into a vector register. |
| v_rsq_f32 | v_rsq_f32 VDST, S0 | VOP1 | Per-lane fast approximate reciprocal square root. |
| v_rsq_f64 | v_rsq_f64 | VOP1 | Calculate the reciprocal of the square root of the double-precision float input using IEEE rules and store the result into a vector register. |
| v_sad_hi_u8 | v_sad_hi_u8 | VOP3 | Calculate the sum of absolute differences of elements in two packed 4-component unsigned 8-bit integer inputs, shift the sum left by 16 bits, add an… |
| v_sad_u16 | v_sad_u16 | VOP3 | Calculate the sum of absolute differences of elements in two packed 2-component unsigned 16-bit integer inputs, add an unsigned 32-bit integer value… |
| v_sad_u32 | v_sad_u32 | VOP3 | Calculate the absolute difference of two unsigned 32-bit integer inputs, add an unsigned 32-bit integer value from the third input and store the… |
| v_sad_u8 | v_sad_u8 | VOP3 | Calculate the sum of absolute differences of elements in two packed 4-component unsigned 8-bit integer inputs, add an unsigned 32-bit integer value… |
| v_sat_pk4_i4_i8 | v_sat_pk4_i4_i8 | VOP1 | AMDGPU VOP1 vector instruction operating on i8 data. (Format and name extracted from LLVM's AMDGPU backend source - semantics not yet curated.) |
| v_sat_pk4_u4_u8 | v_sat_pk4_u4_u8 | VOP1 | AMDGPU VOP1 vector instruction operating on u8 data. (Format and name extracted from LLVM's AMDGPU backend source - semantics not yet curated.) |
| v_sat_pk_u8_i16 | v_sat_pk_u8_i16 | VOP1 | Given 2 signed 16-bit integer inputs, saturate each input over an unsigned 8-bit integer range, pack the resulting values into a packed 16-bit value… |
| v_screen_partition_4se_b32 | v_screen_partition_4se_b32 | VOP1 | 4SE version of LUT instruction for screen partitioning/filtering. |
| v_sin_bf16 | v_sin_bf16 | VOP1 | AMDGPU VOP1 vector instruction. (Format and name extracted from LLVM's AMDGPU backend source - semantics not yet curated.) |
| v_sin_f16 | v_sin_f16 | VOP1 | Calculate the trigonometric sine of a half-precision float value using IEEE rules and store the result into a vector register. |
| v_sin_f32 | v_sin_f32 VDST, S0 | VOP1 | Per-lane fast approximate sine. |
| v_sqrt_bf16 | v_sqrt_bf16 | VOP1 | AMDGPU VOP1 vector instruction. (Format and name extracted from LLVM's AMDGPU backend source - semantics not yet curated.) |
| v_sqrt_f16 | v_sqrt_f16 | VOP1 | Calculate the square root of the half-precision float input using IEEE rules and store the result into a vector register. |
| v_sqrt_f32 | v_sqrt_f32 | VOP1 | Calculate the square root of the single-precision float input using IEEE rules and store the result into a vector register. |
| v_sqrt_f64 | v_sqrt_f64 | VOP1 | Calculate the square root of the double-precision float input using IEEE rules and store the result into a vector register. |
| v_sub_co_ci_u32 | v_sub_co_ci_u32 | VOP2 | Subtract the second unsigned 32-bit integer input from the first input, subtract a bit from the carry-in mask, store the result into a vector… |
| v_sub_co_u32 | v_sub_co_u32 | VOP2 | Subtract the second unsigned 32-bit integer input from the first input, store the result into a vector register and store the carry-out mask into a… |
| v_sub_f16 | v_sub_f16 | VOP2 | Subtract the second floating point input from the first input and store the result into a vector register. |
| v_sub_f32 | v_sub_f32 VDST, S0, S1 | VOP2 | Per-lane single-precision floating-point subtract. |
| v_sub_i16 | v_sub_i16 | VOP3 | Subtract the second signed 16-bit integer input from the first input and store the result into a vector register. No carry-in or carry-out support. |
| v_sub_i32 | v_sub_i32 | VOP2 | Subtract the second signed 32-bit integer input from the first input and store the result into a vector register. No carry-in or carry-out support. |
| v_sub_nc_i16 | v_sub_nc_i16 | VOP3 | Subtract the second signed 16-bit integer input from the first input and store the result into a vector register. No carry-in or carry-out support. |
| v_sub_nc_i32 | v_sub_nc_i32 | VOP3 | Subtract the second signed 32-bit integer input from the first input and store the result into a vector register. No carry-in or carry-out support. |
| v_sub_nc_u16 | v_sub_nc_u16 | VOP3 | Subtract the second unsigned 16-bit integer input from the first input and store the result into a vector register. No carry-in or carry-out support. |
| v_sub_nc_u32 | v_sub_nc_u32 | VOP2 | Subtract the second unsigned 32-bit integer input from the first input and store the result into a vector register. No carry-in or carry-out support. |
| v_sub_nc_u64 | v_sub_nc_u64 | VOP2 | AMDGPU VOP2 vector instruction operating on u64 data. (Format and name extracted from LLVM's AMDGPU backend source - semantics not yet curated.) |
| v_sub_u16 | v_sub_u16 | VOP2 | Subtract the second unsigned 16-bit integer input from the first input and store the result into a vector register. No carry-in or carry-out support. |
| v_sub_u32 | v_sub_u32 | VOP2 | Subtract the second unsigned 32-bit integer input from the first input and store the result into a vector register. No carry-in or carry-out support. |
| v_subb_co_u32 | v_subb_co_u32 | VOP2 | Subtract the second unsigned 32-bit integer input from the first input, subtract a bit from the carry-in mask, store the result into a vector… |
| v_subb_u32 | v_subb_u32 | VOP2 | AMDGPU VOP2 vector instruction operating on u32 data. (Format and name extracted from LLVM's AMDGPU backend source - semantics not yet curated.) |
| v_subbrev_co_u32 | v_subbrev_co_u32 | VOP2 | Subtract the first unsigned 32-bit integer input from the second input, subtract a bit from the carry-in mask, store the result into a vector… |
| v_subbrev_u32 | v_subbrev_u32 | VOP2 | AMDGPU VOP2 vector instruction operating on u32 data. (Format and name extracted from LLVM's AMDGPU backend source - semantics not yet curated.) |
| v_subrev_co_ci_u32 | v_subrev_co_ci_u32 | VOP2 | Subtract the first unsigned 32-bit integer input from the second input, subtract a bit from the carry-in mask, store the result into a vector… |
| v_subrev_co_u32 | v_subrev_co_u32 | VOP2 | Subtract the first unsigned 32-bit integer input from the second input, store the result into a vector register and store the carry-out mask into a… |
| v_subrev_f16 | v_subrev_f16 | VOP2 | Subtract the first floating point input from the second input and store the result into a vector register. |
| v_subrev_f32 | v_subrev_f32 | VOP2 | Subtract the first floating point input from the second input and store the result into a vector register. |
| v_subrev_i32 | v_subrev_i32 | VOP2 | AMDGPU VOP2 vector instruction operating on i32 data. (Format and name extracted from LLVM's AMDGPU backend source - semantics not yet curated.) |
| v_subrev_nc_u32 | v_subrev_nc_u32 | VOP2 | Subtract the first unsigned 32-bit integer input from the second input and store the result into a vector register. No carry-in or carry-out support. |
| v_subrev_u16 | v_subrev_u16 | VOP2 | Subtract the first unsigned 16-bit integer input from the second input and store the result into a vector register. No carry-in or carry-out support. |
| v_subrev_u32 | v_subrev_u32 | VOP2 | Subtract the first unsigned 32-bit integer input from the second input and store the result into a vector register. No carry-in or carry-out support. |
| v_swap_b16 | v_swap_b16 | VOP1 | Swap the values in two vector registers. |
| v_swap_b32 | v_swap_b32 | VOP1 | Swap the values in two vector registers. |
| v_swaprel_b32 | v_swaprel_b32 | VOP1 | Swap the values in two relatively-indexed vector registers. |
| v_tanh_bf16 | v_tanh_bf16 | VOP1 | AMDGPU VOP1 vector instruction. (Format and name extracted from LLVM's AMDGPU backend source - semantics not yet curated.) |
| v_tanh_f16 | v_tanh_f16 | VOP1 | AMDGPU VOP1 vector instruction operating on f16 data. (Format and name extracted from LLVM's AMDGPU backend source - semantics not yet curated.) |
| v_tanh_f32 | v_tanh_f32 | VOP1 | AMDGPU VOP1 vector instruction operating on f32 data. (Format and name extracted from LLVM's AMDGPU backend source - semantics not yet curated.) |
| v_trig_preop_f64 | v_trig_preop_f64 | VOP3 | Look up a 53-bit segment of 2/PI using an integer segment select in the second input. |
| v_trunc_f16 | v_trunc_f16 | VOP1 | Compute the integer part of a half-precision float input using round toward zero semantics and store the result in floating point format into a… |
| v_trunc_f32 | v_trunc_f32 | VOP1 | Compute the integer part of a single-precision float input using round toward zero semantics and store the result in floating point format into a… |
| v_trunc_f64 | v_trunc_f64 | VOP1 | Compute the integer part of a double-precision float input using round toward zero semantics and store the result in floating point format into a… |
| v_writelane_b32 | v_writelane_b32 | VOP2 | Write the scalar value in the first input into the specified lane of a vector register where the lane select is in the second input. |
| v_xad_u32 | v_xad_u32 | VOP3 | Calculate bitwise XOR of the first two vector inputs, then add the third vector input to the intermediate result, then store the final result into a… |
| v_xnor_b32 | v_xnor_b32 | VOP2 | Calculate bitwise XNOR on two vector inputs and store the result into a vector register. |
| v_xor3_b32 | v_xor3_b32 | VOP3 | Calculate the bitwise XOR of three vector inputs and store the result into a vector register. |
| v_xor_b16 | v_xor_b16 | VOP3 | Calculate bitwise XOR on two vector inputs and store the result into a vector register. |
| v_xor_b16_fake16 | v_xor_b16_fake16 | VOP2 | AMDGPU VOP2 vector instruction operating on b16 data. (Format and name extracted from LLVM's AMDGPU backend source - semantics not yet curated.) |
| v_xor_b16_t16 | v_xor_b16_t16 | VOP2 | AMDGPU VOP2 vector instruction operating on b16 data. (Format and name extracted from LLVM's AMDGPU backend source - semantics not yet curated.) |
| v_xor_b32 | v_xor_b32 | VOP2 | Calculate bitwise XOR on two vector inputs and store the result into a vector register. |