Vector Arithmetic Instructions
558 AMDGPU instructions in this category - showing 100 per page, page 5 of 6 - click any row for encoding, pseudocode, and full documentation.
| Mnemonic | Syntax | Format | Summary |
|---|---|---|---|
| v_med3_num_f32 | v_med3_num_f32 | VOP3 | Select the median of three single-precision float inputs and store the selected value into a vector register. |
| v_med3_u16 | v_med3_u16 | VOP3 | Select the median of three unsigned 16-bit integer values and store the selected value into a vector register. |
| v_med3_u32 | v_med3_u32 | VOP3 | Select the median of three unsigned 32-bit integer values and store the selected value into a vector register. |
| v_min3_f16 | v_min3_f16 | VOP3 | Select the minimum of three half-precision float inputs and store the selected value into a vector register. |
| v_min3_f32 | v_min3_f32 | VOP3 | Select the minimum of three single-precision float inputs and store the selected value into a vector register. |
| v_min3_i16 | v_min3_i16 | VOP3 | Select the minimum of three signed 16-bit integer inputs and store the selected value into a vector register. |
| v_min3_i32 | v_min3_i32 | VOP3 | Select the minimum of three signed 32-bit integer inputs and store the selected value into a vector register. |
| v_min3_num_f16 | v_min3_num_f16 | VOP3 | Select the IEEE minimumNumber() of three half-precision float inputs and store the selected value into a vector register. |
| v_min3_num_f32 | v_min3_num_f32 | VOP3 | Select the IEEE minimumNumber() of three single-precision float inputs and store the selected value into a vector register. |
| v_min3_u16 | v_min3_u16 | VOP3 | Select the minimum of three unsigned 16-bit integer inputs and store the selected value into a vector register. |
| v_min3_u32 | v_min3_u32 | VOP3 | Select the minimum of three unsigned 32-bit integer inputs and store the selected value into a vector register. |
| v_min_f16 | v_min_f16 | VOP2 | Select the minimum of two half-precision float inputs and store the result into a vector register. |
| v_min_f32 | v_min_f32 | VOP2 | Select the minimum of two single-precision float inputs and store the result into a vector register. |
| v_min_f64 | v_min_f64 | VOP2 | Select the minimum of two double-precision float inputs and store the selected value into a vector register. |
| v_min_i16 | v_min_i16 | VOP2 | Select the minimum of two signed 16-bit integer inputs and store the selected value into a vector register. |
| v_min_i32 | v_min_i32 | VOP2 | Select the minimum of two signed 32-bit integer inputs and store the selected value into a vector register. |
| v_min_i64 | v_min_i64 | VOP3 | AMDGPU VOP3 vector instruction operating on i64 data. (Format and name extracted from LLVM's AMDGPU backend source - semantics not yet curated.) |
| v_min_legacy_f32 | v_min_legacy_f32 | VOP2 | AMDGPU VOP2 vector instruction operating on f32 data. (Format and name extracted from LLVM's AMDGPU backend source - semantics not yet curated.) |
| v_min_num_f16 | v_min_num_f16 | VOP2 | Select the IEEE minimumNumber() of two half-precision float inputs and store the selected value into a vector register. |
| v_min_num_f32 | v_min_num_f32 | VOP2 | Select the IEEE minimumNumber() of two single-precision float inputs and store the selected value into a vector register. |
| v_min_num_f64 | v_min_num_f64 | VOP2 | Select the IEEE minimumNumber() of two double-precision float inputs and store the selected value into a vector register. |
| v_min_u16 | v_min_u16 | VOP2 | Select the minimum of two unsigned 16-bit integer inputs and store the selected value into a vector register. |
| v_min_u32 | v_min_u32 | VOP2 | Select the minimum of two unsigned 32-bit integer inputs and store the selected value into a vector register. |
| v_min_u64 | v_min_u64 | VOP3 | AMDGPU VOP3 vector instruction operating on u64 data. (Format and name extracted from LLVM's AMDGPU backend source - semantics not yet curated.) |
| v_minimum3_f16 | v_minimum3_f16 | VOP3 | Select the IEEE minimum() of three half-precision float inputs and store the selected value into a vector register. |
| v_minimum3_f32 | v_minimum3_f32 | VOP3 | Select the IEEE minimum() of three single-precision float inputs and store the result into a vector register. |
| v_minimum_f16 | v_minimum_f16 | VOP3 | Select the IEEE minimum() of two half-precision float inputs and store the selected value into a vector register. |
| v_minimum_f32 | v_minimum_f32 | VOP3 | Select the IEEE minimum() of two single-precision float inputs and store the selected value into a vector register. |
| v_minimum_f64 | v_minimum_f64 | VOP3 | Select the IEEE minimum() of two double-precision float inputs and store the selected value into a vector register. |
| v_minimummaximum_f16 | v_minimummaximum_f16 | VOP3 | Select the IEEE minimum() of the first two half-precision float inputs and then select the IEEE maximum() of that result and third half-precision… |
| v_minimummaximum_f32 | v_minimummaximum_f32 | VOP3 | Select the IEEE minimum() of the first two single-precision float inputs and then select the IEEE maximum() of that result and third single-precision… |
| v_minmax_f16 | v_minmax_f16 | VOP3 | Select the minimum of the first two half-precision float inputs and then select the maximum of that result and third half-precision float input. |
| v_minmax_f32 | v_minmax_f32 | VOP3 | Select the minimum of the first two single-precision float inputs and then select the maximum of that result and third single-precision float input. |
| v_minmax_i32 | v_minmax_i32 | VOP3 | Select the minimum of the first two signed 32-bit integer inputs and then select the maximum of that result and third signed 32-bit integer input. |
| v_minmax_num_f16 | v_minmax_num_f16 | VOP3 | Select the IEEE minimumNumber() of the first two half-precision float inputs and then select the IEEE maximumNumber() of that result and third… |
| v_minmax_num_f32 | v_minmax_num_f32 | VOP3 | Select the IEEE minimumNumber() of the first two single-precision float inputs and then select the IEEE maximumNumber() of that result and third… |
| v_minmax_u32 | v_minmax_u32 | VOP3 | Select the minimum of the first two unsigned 32-bit integer inputs and then select the maximum of that result and third unsigned 32-bit integer input. |
| v_mov_b16 | v_mov_b16 | VOP1 | Move 16-bit data from a vector input into a vector register. |
| v_mov_b32 | v_mov_b32 | VOP1 | Move 32-bit data from a vector input into a vector register. |
| v_mov_b64 | v_mov_b64 | VOP1 | Move data from a 64-bit vector input into a vector register. |
| v_movreld_b32 | v_movreld_b32 | VOP1 | Move data from a vector input into a relatively-indexed vector register. |
| v_movrels_b32 | v_movrels_b32 | VOP1 | Move data from a relatively-indexed vector register into another vector register. |
| v_movrelsd_b32 | v_movrelsd_b32 | VOP1 | Move data from a relatively-indexed vector register into another relatively-indexed vector register. |
| v_mqsad_pk_u16_u8 | v_mqsad_pk_u16_u8 | VOP3 | Perform the V_MSAD_U8 operation four times using different slices of the first array, all entries of the second array and each entry of the third… |
| v_mqsad_u32_u8 | v_mqsad_u32_u8 | VOP3 | Perform the V_MSAD_U8 operation four times using different slices of the first array, all entries of the second array and each entry of the third… |
| v_msad_u8 | v_msad_u8 | VOP3 | Calculate the sum of absolute differences of elements in two packed 4-component unsigned 8-bit integer inputs, except that elements where the second… |
| v_mul_f16 | v_mul_f16 | VOP2 | Multiply two floating point inputs and store the result into a vector register. |
| v_mul_f32 | v_mul_f32 VDST, S0, S1 | VOP2 | Per-lane single-precision floating-point multiply. |
| v_mul_f64 | v_mul_f64 | VOP2 | Multiply two floating point inputs and store the result into a vector register. |
| v_mul_f64_pseudo | v_mul_f64_pseudo | VOP2 | AMDGPU VOP2 vector instruction operating on f64 data. (Format and name extracted from LLVM's AMDGPU backend source - semantics not yet curated.) |
| v_mul_hi_i32 | v_mul_hi_i32 | VOP3 | Multiply two signed 32-bit integer inputs and store the high 32 bits of the result into a vector register. |
| v_mul_hi_i32_i24 | v_mul_hi_i32_i24 | VOP2 | Multiply two signed 24-bit integer inputs and store the high 32 bits of the result as a signed 32-bit integer into a vector register. |
| v_mul_hi_u32 | v_mul_hi_u32 | VOP3 | Multiply two unsigned 32-bit integer inputs and store the high 32 bits of the result into a vector register. |
| v_mul_hi_u32_u24 | v_mul_hi_u32_u24 | VOP2 | Multiply two unsigned 24-bit integer inputs and store the high 32 bits of the result as an unsigned 32-bit integer into a vector register. |
| v_mul_i32_i24 | v_mul_i32_i24 | VOP2 | Multiply two signed 24-bit integer inputs and store the result as a signed 32-bit integer into a vector register. |
| v_mul_legacy_f32 | v_mul_legacy_f32 | VOP2 | Multiply two floating point inputs and store the result into a vector register. |
| v_mul_lo_i32 | v_mul_lo_i32 | VOP3 | AMDGPU VOP3 vector instruction operating on i32 data. (Format and name extracted from LLVM's AMDGPU backend source - semantics not yet curated.) |
| v_mul_lo_u16 | v_mul_lo_u16 | VOP2 | Multiply two unsigned 16-bit integer inputs and store the low bits of the result into a vector register. |
| v_mul_lo_u32 | v_mul_lo_u32 VDST, S0, S1 | VOP3 | Per-lane 32-bit unsigned multiply, low half of the product. |
| v_mul_u32_u24 | v_mul_u32_u24 | VOP2 | Multiply two unsigned 24-bit integer inputs and store the result as an unsigned 32-bit integer into a vector register. |
| v_mul_u64 | v_mul_u64 | VOP2 | AMDGPU VOP2 vector instruction operating on u64 data. (Format and name extracted from LLVM's AMDGPU backend source - semantics not yet curated.) |
| v_mullit_f32 | v_mullit_f32 | VOP3 | Multiply two floating point inputs and store the result into a vector register. |
| v_nop | v_nop | VOP1 | Do nothing. |
| v_not_b16 | v_not_b16 | VOP1 | Calculate bitwise negation on a vector input and store the result into a vector register. |
| v_not_b32 | v_not_b32 | VOP1 | Calculate bitwise negation on a vector input and store the result into a vector register. |
| v_or3_b32 | v_or3_b32 | VOP3 | Calculate the bitwise OR of three vector inputs and store the result into a vector register. |
| v_or_b16 | v_or_b16 | VOP3 | Calculate bitwise OR on two vector inputs and store the result into a vector register. |
| v_or_b16_fake16 | v_or_b16_fake16 | VOP2 | AMDGPU VOP2 vector instruction operating on b16 data. (Format and name extracted from LLVM's AMDGPU backend source - semantics not yet curated.) |
| v_or_b16_t16 | v_or_b16_t16 | VOP2 | AMDGPU VOP2 vector instruction operating on b16 data. (Format and name extracted from LLVM's AMDGPU backend source - semantics not yet curated.) |
| v_or_b32 | v_or_b32 | VOP2 | Calculate bitwise OR on two vector inputs and store the result into a vector register. |
| v_pack_b32_f16 | v_pack_b32_f16 | VOP3 | Pack two half-precision float values into a single 32-bit value and store the result into a vector register. |
| v_perm_b32 | v_perm_b32 | VOP3 | Permute a 64-bit value constructed from two vector inputs (most significant bits come from the first input) using a per-lane selector from the third… |
| v_perm_pk16_b4_u4 | v_perm_pk16_b4_u4 | VOP3 | AMDGPU VOP3 vector instruction. (Format and name extracted from LLVM's AMDGPU backend source - semantics not yet curated.) |
| v_perm_pk16_b6_u4 | v_perm_pk16_b6_u4 | VOP3 | AMDGPU VOP3 vector instruction. (Format and name extracted from LLVM's AMDGPU backend source - semantics not yet curated.) |
| v_perm_pk16_b8_u4 | v_perm_pk16_b8_u4 | VOP3 | AMDGPU VOP3 vector instruction operating on b8 data. (Format and name extracted from LLVM's AMDGPU backend source - semantics not yet curated.) |
| v_permlane16_b32 | v_permlane16_b32 | VOP3 | Perform arbitrary gather-style operation within a row (16 contiguous lanes). |
| v_permlane16_swap_b32 | v_permlane16_swap_b32 | VOP1 | Swap data between two vector registers. Odd rows of the first operand are swapped with even rows of the second operand (one row is 16 lanes). |
| v_permlane16_var_b32 | v_permlane16_var_b32 | VOP3 | Perform arbitrary gather-style operation within a row (16 contiguous lanes). |
| v_permlane32_swap_b32 | v_permlane32_swap_b32 | VOP1 | Swap data between two vector registers. Rows 2 and 3 of the first operand are swapped with rows 0 and 1 of the second operand (one row is 16 lanes). |
| v_permlane64_b32 | v_permlane64_b32 | VOP1 | Perform a specific permutation across lanes where the high half and low half of a wave64 are swapped. Performs no operation in wave32 mode. |
| v_permlane_bcast_b32 | v_permlane_bcast_b32 | VOP3 | AMDGPU VOP3 vector instruction operating on b32 data. (Format and name extracted from LLVM's AMDGPU backend source - semantics not yet curated.) |
| v_permlane_down_b32 | v_permlane_down_b32 | VOP3 | AMDGPU VOP3 vector instruction operating on b32 data. (Format and name extracted from LLVM's AMDGPU backend source - semantics not yet curated.) |
| v_permlane_idx_gen_b32 | v_permlane_idx_gen_b32 | VOP3 | AMDGPU VOP3 vector instruction operating on b32 data. (Format and name extracted from LLVM's AMDGPU backend source - semantics not yet curated.) |
| v_permlane_up_b32 | v_permlane_up_b32 | VOP3 | AMDGPU VOP3 vector instruction operating on b32 data. (Format and name extracted from LLVM's AMDGPU backend source - semantics not yet curated.) |
| v_permlane_xor_b32 | v_permlane_xor_b32 | VOP3 | AMDGPU VOP3 vector instruction operating on b32 data. (Format and name extracted from LLVM's AMDGPU backend source - semantics not yet curated.) |
| v_permlanex16_b32 | v_permlanex16_b32 | VOP3 | Perform arbitrary gather-style operation across two rows (each row is 16 contiguous lanes). |
| v_permlanex16_var_b32 | v_permlanex16_var_b32 | VOP3 | Perform arbitrary gather-style operation across two rows (each row is 16 contiguous lanes). |
| v_pipeflush | v_pipeflush | VOP1 | Flush the vector ALU pipeline through the destination cache. |
| v_pk_fmac_f16 | v_pk_fmac_f16 | VOP2 | Multiply two packed half-precision float inputs component-wise and accumulate the result into the destination register using fused multiply add. |
| v_prng_b32 | v_prng_b32 | VOP1 | Generate a pseudorandom number using an LFSR (linear feedback shift register) seeded with the vector input, then store the result into a vector… |
| v_qsad_pk_u16_u8 | v_qsad_pk_u16_u8 | VOP3 | Perform the V_SAD_U8 operation four times using different slices of the first array, all entries of the second array and each entry of the third… |
| v_rcp_bf16 | v_rcp_bf16 | VOP1 | AMDGPU VOP1 vector instruction. (Format and name extracted from LLVM's AMDGPU backend source - semantics not yet curated.) |
| v_rcp_f16 | v_rcp_f16 | VOP1 | Calculate the reciprocal of the half-precision float input using IEEE rules and store the result into a vector register. |
| v_rcp_f32 | v_rcp_f32 | VOP1 | Calculate the reciprocal of the single-precision float input using IEEE rules and store the result into a vector register. |
| v_rcp_f64 | v_rcp_f64 | VOP1 | Calculate the reciprocal of the double-precision float input using IEEE rules and store the result into a vector register. |
| v_rcp_iflag_f32 | v_rcp_iflag_f32 | VOP1 | Calculate the reciprocal of the vector float input in a manner suitable for integer division and store the result into a vector register. |
| v_readlane_b32 | v_readlane_b32 | VOP2 | Read the scalar value in the specified lane of the first input where the lane select is in the second input. Store the result into a scalar register. |
| v_rndne_f16 | v_rndne_f16 | VOP1 | Round the half-precision float input to the nearest even integer and store the result in floating point format into a vector register. |
| v_rndne_f32 | v_rndne_f32 | VOP1 | Round the single-precision float input to the nearest even integer and store the result in floating point format into a vector register. |
| v_rndne_f64 | v_rndne_f64 | VOP1 | Round the double-precision float input to the nearest even integer and store the result in floating point format into a vector register. |