Vector Arithmetic Instructions
597 AMDGPU instructions in this category - showing 100 per page, page 3 of 6 - click any row for encoding, pseudocode, and full documentation.
| Mnemonic | Syntax | Format | Summary |
|---|---|---|---|
| v_cvt_scalef32_sr_bf8_f32 | v_cvt_scalef32_sr_bf8_f32 | VOP3 | Scale a single-precision float input using the exponent provided by the third single-precision float input, then convert the values to a BF8 float… |
| v_cvt_scalef32_sr_fp8_bf16 | v_cvt_scalef32_sr_fp8_bf16 | VOP3 | Scale a BF16 float input using the exponent provided by the third single-precision float input, then convert the values to an FP8 float value with… |
| v_cvt_scalef32_sr_fp8_f16 | v_cvt_scalef32_sr_fp8_f16 | VOP3 | Scale a half-precision float input using the exponent provided by the third single-precision float input, then convert the values to an FP8 float… |
| v_cvt_scalef32_sr_fp8_f32 | v_cvt_scalef32_sr_fp8_f32 | VOP3 | Scale a single-precision float input using the exponent provided by the third single-precision float input, then convert the values to an FP8 float… |
| v_cvt_scalef32_sr_pk16_bf6_bf16 | v_cvt_scalef32_sr_pk16_bf6_bf16 | VOP3 | AMDGPU VOP3 vector instruction. (Format and name extracted from LLVM's AMDGPU backend source - semantics not yet curated.) |
| v_cvt_scalef32_sr_pk16_bf6_f16 | v_cvt_scalef32_sr_pk16_bf6_f16 | VOP3 | AMDGPU VOP3 vector instruction operating on f16 data. (Format and name extracted from LLVM's AMDGPU backend source - semantics not yet curated.) |
| v_cvt_scalef32_sr_pk16_bf6_f32 | v_cvt_scalef32_sr_pk16_bf6_f32 | VOP3 | AMDGPU VOP3 vector instruction operating on f32 data. (Format and name extracted from LLVM's AMDGPU backend source - semantics not yet curated.) |
| v_cvt_scalef32_sr_pk16_fp6_bf16 | v_cvt_scalef32_sr_pk16_fp6_bf16 | VOP3 | AMDGPU VOP3 vector instruction. (Format and name extracted from LLVM's AMDGPU backend source - semantics not yet curated.) |
| v_cvt_scalef32_sr_pk16_fp6_f16 | v_cvt_scalef32_sr_pk16_fp6_f16 | VOP3 | AMDGPU VOP3 vector instruction operating on f16 data. (Format and name extracted from LLVM's AMDGPU backend source - semantics not yet curated.) |
| v_cvt_scalef32_sr_pk16_fp6_f32 | v_cvt_scalef32_sr_pk16_fp6_f32 | VOP3 | AMDGPU VOP3 vector instruction operating on f32 data. (Format and name extracted from LLVM's AMDGPU backend source - semantics not yet curated.) |
| v_cvt_scalef32_sr_pk32_bf6_bf16 | v_cvt_scalef32_sr_pk32_bf6_bf16 | VOP3 | Scale a packed 32-component BF16 float input using the exponent provided by the third single-precision float input, then convert the values to a… |
| v_cvt_scalef32_sr_pk32_bf6_f16 | v_cvt_scalef32_sr_pk32_bf6_f16 | VOP3 | Scale a packed 32-component half-precision float input using the exponent provided by the third single-precision float input, then convert the values… |
| v_cvt_scalef32_sr_pk32_bf6_f32 | v_cvt_scalef32_sr_pk32_bf6_f32 | VOP3 | Scale a packed 32-component single-precision float input using the exponent provided by the third single-precision float input, then convert the… |
| v_cvt_scalef32_sr_pk32_fp6_bf16 | v_cvt_scalef32_sr_pk32_fp6_bf16 | VOP3 | Scale a packed 32-component BF16 float input using the exponent provided by the third single-precision float input, then convert the values to a… |
| v_cvt_scalef32_sr_pk32_fp6_f16 | v_cvt_scalef32_sr_pk32_fp6_f16 | VOP3 | Scale a packed 32-component half-precision float input using the exponent provided by the third single-precision float input, then convert the values… |
| v_cvt_scalef32_sr_pk32_fp6_f32 | v_cvt_scalef32_sr_pk32_fp6_f32 | VOP3 | Scale a packed 32-component single-precision float input using the exponent provided by the third single-precision float input, then convert the… |
| v_cvt_scalef32_sr_pk8_bf8_bf16 | v_cvt_scalef32_sr_pk8_bf8_bf16 | VOP3 | AMDGPU VOP3 vector instruction. (Format and name extracted from LLVM's AMDGPU backend source - semantics not yet curated.) |
| v_cvt_scalef32_sr_pk8_bf8_f16 | v_cvt_scalef32_sr_pk8_bf8_f16 | VOP3 | AMDGPU VOP3 vector instruction operating on f16 data. (Format and name extracted from LLVM's AMDGPU backend source - semantics not yet curated.) |
| v_cvt_scalef32_sr_pk8_bf8_f32 | v_cvt_scalef32_sr_pk8_bf8_f32 | VOP3 | AMDGPU VOP3 vector instruction operating on f32 data. (Format and name extracted from LLVM's AMDGPU backend source - semantics not yet curated.) |
| v_cvt_scalef32_sr_pk8_fp4_bf16 | v_cvt_scalef32_sr_pk8_fp4_bf16 | VOP3 | AMDGPU VOP3 vector instruction. (Format and name extracted from LLVM's AMDGPU backend source - semantics not yet curated.) |
| v_cvt_scalef32_sr_pk8_fp4_f16 | v_cvt_scalef32_sr_pk8_fp4_f16 | VOP3 | AMDGPU VOP3 vector instruction operating on f16 data. (Format and name extracted from LLVM's AMDGPU backend source - semantics not yet curated.) |
| v_cvt_scalef32_sr_pk8_fp4_f32 | v_cvt_scalef32_sr_pk8_fp4_f32 | VOP3 | AMDGPU VOP3 vector instruction operating on f32 data. (Format and name extracted from LLVM's AMDGPU backend source - semantics not yet curated.) |
| v_cvt_scalef32_sr_pk8_fp8_bf16 | v_cvt_scalef32_sr_pk8_fp8_bf16 | VOP3 | AMDGPU VOP3 vector instruction. (Format and name extracted from LLVM's AMDGPU backend source - semantics not yet curated.) |
| v_cvt_scalef32_sr_pk8_fp8_f16 | v_cvt_scalef32_sr_pk8_fp8_f16 | VOP3 | AMDGPU VOP3 vector instruction operating on f16 data. (Format and name extracted from LLVM's AMDGPU backend source - semantics not yet curated.) |
| v_cvt_scalef32_sr_pk8_fp8_f32 | v_cvt_scalef32_sr_pk8_fp8_f32 | VOP3 | AMDGPU VOP3 vector instruction operating on f32 data. (Format and name extracted from LLVM's AMDGPU backend source - semantics not yet curated.) |
| v_cvt_scalef32_sr_pk_fp4_bf16 | v_cvt_scalef32_sr_pk_fp4_bf16 | VOP3 | Scale a packed 2-component BF16 float input using the exponent provided by the third single-precision float input, then convert the values to a… |
| v_cvt_scalef32_sr_pk_fp4_f16 | v_cvt_scalef32_sr_pk_fp4_f16 | VOP3 | Scale a packed 2-component half-precision float input using the exponent provided by the third single-precision float input, then convert the values… |
| v_cvt_scalef32_sr_pk_fp4_f32 | v_cvt_scalef32_sr_pk_fp4_f32 | VOP3 | Scale a packed 2-component single-precision float input using the exponent provided by the third single-precision float input, then convert the… |
| v_cvt_sr_bf16_f32 | v_cvt_sr_bf16_f32 | VOP3 | Convert from a single-precision float input to a BF16 value with stochastic rounding using seed data from the second input. |
| v_cvt_sr_bf8_f16 | v_cvt_sr_bf8_f16 | VOP3 | AMDGPU VOP3 vector instruction operating on f16 data. (Format and name extracted from LLVM's AMDGPU backend source - semantics not yet curated.) |
| v_cvt_sr_bf8_f32 | v_cvt_sr_bf8_f32 | VOP3 | Convert from a single-precision float input to a BF8 value with stochastic rounding using seed data from the second input. |
| v_cvt_sr_bf8_f32_gfx12 | v_cvt_sr_bf8_f32_gfx12 | VOP3 | AMDGPU VOP3 vector instruction operating on f32 data. (Format and name extracted from LLVM's AMDGPU backend source - semantics not yet curated.) |
| v_cvt_sr_f16_f32 | v_cvt_sr_f16_f32 | VOP3 | Convert from a single-precision float input to a half-precision value with stochastic rounding using seed data from the second input. |
| v_cvt_sr_fp8_f16 | v_cvt_sr_fp8_f16 | VOP3 | AMDGPU VOP3 vector instruction operating on f16 data. (Format and name extracted from LLVM's AMDGPU backend source - semantics not yet curated.) |
| v_cvt_sr_fp8_f32 | v_cvt_sr_fp8_f32 | VOP3 | Convert from a single-precision float input to an FP8 value with stochastic rounding using seed data from the second input. |
| v_cvt_sr_fp8_f32_gfx12 | v_cvt_sr_fp8_f32_gfx12 | VOP3 | AMDGPU VOP3 vector instruction operating on f32 data. (Format and name extracted from LLVM's AMDGPU backend source - semantics not yet curated.) |
| v_cvt_sr_fp8_f32_gfx1250 | v_cvt_sr_fp8_f32_gfx1250 | VOP3 | AMDGPU VOP3 vector instruction operating on f32 data. (Format and name extracted from LLVM's AMDGPU backend source - semantics not yet curated.) |
| v_cvt_sr_pk_bf16_f32 | v_cvt_sr_pk_bf16_f32 | VOP3 | AMDGPU VOP3 vector instruction operating on f32 data. (Format and name extracted from LLVM's AMDGPU backend source - semantics not yet curated.) |
| v_cvt_sr_pk_f16_f32 | v_cvt_sr_pk_f16_f32 | VOP3 | AMDGPU VOP3 vector instruction operating on f16/f32 data. (Format and name extracted from LLVM's AMDGPU backend source - semantics not yet curated.) |
| v_cvt_u16_f16 | v_cvt_u16_f16 | VOP1 | Convert from a half-precision float input to an unsigned 16-bit integer value and store the result into a vector register. |
| v_cvt_u32_f32 | v_cvt_u32_f32 | VOP1 | Convert from a single-precision float input to an unsigned 32-bit integer value and store the result into a vector register. |
| v_cvt_u32_f64 | v_cvt_u32_f64 | VOP1 | Convert from a double-precision float input to an unsigned 32-bit integer value and store the result into a vector register. |
| v_cvt_u32_u16 | v_cvt_u32_u16 | VOP1 | Convert from an unsigned 16-bit integer input to an unsigned 32-bit integer value using zero extension and store the result into a vector register. |
| v_div_fixup_f16 | v_div_fixup_f16 | VOP3 | Given a half-precision float quotient in the first input, a denominator in the second input and a numerator in the third input, detect and apply… |
| v_div_fixup_f16_gfx9 | v_div_fixup_f16_gfx9 | VOP3 | AMDGPU VOP3 vector instruction operating on f16 data. (Format and name extracted from LLVM's AMDGPU backend source - semantics not yet curated.) |
| v_div_fixup_f32 | v_div_fixup_f32 | VOP3 | Given a single-precision float quotient in the first input, a denominator in the second input and a numerator in the third input, detect and apply… |
| v_div_fixup_f64 | v_div_fixup_f64 | VOP3 | Given a double-precision float quotient in the first input, a denominator in the second input and a numerator in the third input, detect and apply… |
| v_div_fixup_legacy_f16 | v_div_fixup_legacy_f16 | VOP3 | Half precision division fixup. Has non-standard rule for OPSEL. |
| v_div_fmas_f32 | v_div_fmas_f32 | VOP3 | Multiply two single-precision float inputs and add a third input using fused multiply add, then scale the exponent of the result by a fixed factor if… |
| v_div_fmas_f64 | v_div_fmas_f64 | VOP3 | Multiply two double-precision float inputs and add a third input using fused multiply add, then scale the exponent of the result by a fixed factor if… |
| v_div_scale_f32 | v_div_scale_f32 | VOP3 | Given a single-precision float value to scale in the first input, a denominator in the second input and a numerator in the third input, scale the… |
| v_div_scale_f64 | v_div_scale_f64 | VOP3 | Given a double-precision float value to scale in the first input, a denominator in the second input and a numerator in the third input, scale the… |
| v_dot2_bf16_bf16 | v_dot2_bf16_bf16 | VOP3 | Compute the dot product of two packed 2-D BF16 float inputs, add the third input and store the result into a vector register. |
| v_dot2_f16_f16 | v_dot2_f16_f16 | VOP3 | Compute the dot product of two packed 2-D half-precision float inputs, add the third input and store the result into a vector register. |
| v_dot2c_f32_bf16 | v_dot2c_f32_bf16 | VOP2 | Compute the dot product of two packed 2-D BF16 float inputs in the single-precision float domain and accumulate with the single-precision float value… |
| v_dot2c_f32_f16 | v_dot2c_f32_f16 | VOP2 | Compute the dot product of two packed 2-D half-precision float inputs in the single-precision float domain and accumulate with the single-precision… |
| v_dot2c_i32_i16 | v_dot2c_i32_i16 | VOP2 | Compute the dot product of two packed 2-D signed 16-bit integer inputs in the signed 32-bit integer domain and accumulate with the signed 32-bit… |
| v_dot4c_i32_i8 | v_dot4c_i32_i8 | VOP2 | Compute the dot product of two packed 4-D signed 8-bit integer inputs in the signed 32-bit integer domain and accumulate with the signed 32-bit… |
| v_dot8c_i32_i4 | v_dot8c_i32_i4 | VOP2 | Compute the dot product of two packed 8-D signed 4-bit integer inputs in the signed 32-bit integer domain and accumulate with the signed 32-bit… |
| v_dual_add_f32 | v_dual_add_f32 | VOPD | Add two floating point inputs and store the result into a vector register. |
| v_dual_add_f64 | v_dual_add_f64 | VOPD | Add two floating point inputs and store the result into a vector register. |
| v_dual_add_nc_u32 | v_dual_add_nc_u32 | VOPD | Add two unsigned 32-bit integer inputs and store the result into a vector register. No carry-in or carry-out support. |
| v_dual_and_b32 | v_dual_and_b32 | VOPD | Calculate bitwise AND on two vector inputs and store the result into a vector register. |
| v_dual_ashrrev_i32 | v_dual_ashrrev_i32 | VOPD | Given a shift count in the first vector input, calculate the arithmetic shift right (preserving sign bit) of the second vector input and store the… |
| v_dual_bitop2_b32 | v_dual_bitop2_b32 | VOPD | Compute a 2-operand generic bitwise operation using a truth table encoded into the instruction. |
| v_dual_cndmask_b32 | v_dual_cndmask_b32 | VOPD | Copy data from one of two inputs based on the per-lane condition code and store the result into a vector register. |
| v_dual_dot2acc_f32_bf16 | v_dual_dot2acc_f32_bf16 | VOPD | Dot product of packed brain-float values, accumulate with destination. The initial value in D is used as S2. |
| v_dual_dot2acc_f32_f16 | v_dual_dot2acc_f32_f16 | VOPD | Compute the dot product of two packed 2-D half-precision float inputs in the single-precision float domain and accumulate the resulting… |
| v_dual_fma_f32 | v_dual_fma_f32 | VOPD | Multiply two single-precision float inputs and add a third input using fused multiply add, and store the result into a vector register. |
| v_dual_fma_f64 | v_dual_fma_f64 | VOPD | Multiply two double-precision float inputs and add a third input using fused multiply add, and store the result into a vector register. |
| v_dual_fmaak_f32 | v_dual_fmaak_f32 | VOPD | Multiply two single-precision float inputs and add a literal constant using fused multiply add, and store the result into a vector register. |
| v_dual_fmac_f32 | v_dual_fmac_f32 | VOPD | Multiply two single-precision float inputs and accumulate the result into the destination register using fused multiply add. |
| v_dual_fmamk_f32 | v_dual_fmamk_f32 | VOPD | Multiply a single-precision float input with a literal constant and add a second single-precision float input using fused multiply add, and store the… |
| v_dual_lshlrev_b32 | v_dual_lshlrev_b32 | VOPD | Given a shift count in the first vector input, calculate the logical shift left of the second vector input and store the result into a vector… |
| v_dual_lshrrev_b32 | v_dual_lshrrev_b32 | VOPD | Given a shift count in the first vector input, calculate the logical shift right of the second vector input and store the result into a vector… |
| v_dual_max_f32 | v_dual_max_f32 | VOPD | Select the maximum of two single-precision float inputs and store the selected value into a vector register. |
| v_dual_max_i32 | v_dual_max_i32 | VOPD | Select the maximum of two signed 32-bit integer inputs and store the selected value into a vector register. |
| v_dual_max_num_f32 | v_dual_max_num_f32 | VOPD | Select the IEEE maximumNumber() of two single-precision float inputs and store the selected value into a vector register. |
| v_dual_max_num_f64 | v_dual_max_num_f64 | VOPD | Select the IEEE maximumNumber() of two double-precision float inputs and store the selected value into a vector register. |
| v_dual_min_f32 | v_dual_min_f32 | VOPD | Select the minimum of two single-precision float inputs and store the selected value into a vector register. |
| v_dual_min_i32 | v_dual_min_i32 | VOPD | Select the minimum of two signed 32-bit integer inputs and store the selected value into a vector register. |
| v_dual_min_num_f32 | v_dual_min_num_f32 | VOPD | Select the IEEE minimumNumber() of two single-precision float inputs and store the selected value into a vector register. |
| v_dual_min_num_f64 | v_dual_min_num_f64 | VOPD | Select the IEEE minimumNumber() of two double-precision float inputs and store the selected value into a vector register. |
| v_dual_mov_b32 | v_dual_mov_b32 | VOPD | Move 32-bit data from a vector input into a vector register. |
| v_dual_mul_dx9_zero_f32 | v_dual_mul_dx9_zero_f32 | VOPD | Multiply two floating point inputs and store the result into a vector register. |
| v_dual_mul_f32 | v_dual_mul_f32 | VOPD | Multiply two floating point inputs and store the result into a vector register. |
| v_dual_mul_f64 | v_dual_mul_f64 | VOPD | Multiply two floating point inputs and store the result into a vector register. |
| v_dual_sub_f32 | v_dual_sub_f32 | VOPD | Subtract the second floating point input from the first input and store the result into a vector register. |
| v_dual_sub_nc_u32 | v_dual_sub_nc_u32 | VOPD | Subtract the second unsigned 32-bit integer input from the first input and store the result into a vector register. No carry-in or carry-out support. |
| v_dual_subrev_f32 | v_dual_subrev_f32 | VOPD | Subtract the first floating point input from the second input and store the result into a vector register. |
| v_exp_bf16 | v_exp_bf16 | VOP1 | AMDGPU VOP1 vector instruction. (Format and name extracted from LLVM's AMDGPU backend source - semantics not yet curated.) |
| v_exp_f16 | v_exp_f16 | VOP1 | Calculate 2 raised to the power of the half-precision float input and store the result into a vector register. |
| v_exp_f32 | v_exp_f32 | VOP1 | Calculate 2 raised to the power of the single-precision float input and store the result into a vector register. |
| v_exp_legacy_f32 | v_exp_legacy_f32 | VOP1 | AMDGPU VOP1 vector instruction operating on f32 data. (Format and name extracted from LLVM's AMDGPU backend source - semantics not yet curated.) |
| v_ffbh_i32 | v_ffbh_i32 | VOP1 | Count the number of leading bits that are the same as the sign bit of a vector input and store the result into a vector register. |
| v_ffbh_u32 | v_ffbh_u32 | VOP1 | Count the number of leading "0" bits before the first "1" in a vector input and store the result into a vector register. |
| v_ffbl_b32 | v_ffbl_b32 | VOP1 | Count the number of trailing "0" bits before the first "1" in a vector input and store the result into a vector register. |
| v_floor_f16 | v_floor_f16 | VOP1 | Round the half-precision float input down to previous integer and store the result in floating point format into a vector register. |
| v_floor_f32 | v_floor_f32 | VOP1 | Round the single-precision float input down to previous integer and store the result in floating point format into a vector register. |
| v_floor_f64 | v_floor_f64 | VOP1 | Round the double-precision float input down to previous integer and store the result in floating point format into a vector register. |