Vector Arithmetic Instructions
597 AMDGPU instructions in this category - showing 100 per page, page 4 of 6 - click any row for encoding, pseudocode, and full documentation.
| Mnemonic | Syntax | Format | Summary |
|---|---|---|---|
| v_fma_dx9_zero_f32 | v_fma_dx9_zero_f32 | VOP3 | Multiply and add single-precision values. Follows DX9 rules where 0.0 times anything produces 0.0. |
| v_fma_f16 | v_fma_f16 | VOP3 | Multiply two half-precision float inputs and add a third input using fused multiply add, and store the result into a vector register. |
| v_fma_f16_gfx9 | v_fma_f16_gfx9 | VOP3 | AMDGPU VOP3 vector instruction operating on f16 data. (Format and name extracted from LLVM's AMDGPU backend source - semantics not yet curated.) |
| v_fma_f32 | v_fma_f32 VDST, S0, S1, S2 | VOP3 | Per-lane single-precision fused multiply-add. |
| v_fma_f64 | v_fma_f64 | VOP3 | Multiply two double-precision float inputs and add a third input using fused multiply add, and store the result into a vector register. |
| v_fma_legacy_f16 | v_fma_legacy_f16 | VOP3 | Fused half precision multiply add. Implements IEEE rules and non-standard rule for OPSEL. |
| v_fma_legacy_f32 | v_fma_legacy_f32 | VOP3 | Multiply and add single-precision values. Follows DX9 rules where 0.0 times anything produces 0.0. |
| v_fmaak_f16 | v_fmaak_f16 | VOP2 | Multiply two half-precision float inputs and add a literal constant using fused multiply add, and store the result into a vector register. |
| v_fmaak_f16_fake16 | v_fmaak_f16_fake16 | VOP2 | AMDGPU VOP2 vector instruction operating on f16 data. (Format and name extracted from LLVM's AMDGPU backend source - semantics not yet curated.) |
| v_fmaak_f16_t16 | v_fmaak_f16_t16 | VOP2 | AMDGPU VOP2 vector instruction operating on f16 data. (Format and name extracted from LLVM's AMDGPU backend source - semantics not yet curated.) |
| v_fmaak_f32 | v_fmaak_f32 | VOP2 | Multiply two single-precision float inputs and add a literal constant using fused multiply add, and store the result into a vector register. |
| v_fmaak_f64 | v_fmaak_f64 | VOP2 | AMDGPU VOP2 vector instruction operating on f64 data. (Format and name extracted from LLVM's AMDGPU backend source - semantics not yet curated.) |
| v_fmac_f16 | v_fmac_f16 | VOP2 | Multiply two half-precision float inputs and accumulate the result into the destination register using fused multiply add. |
| v_fmac_f16_fake16 | v_fmac_f16_fake16 | VOP2 | AMDGPU VOP2 vector instruction operating on f16 data. (Format and name extracted from LLVM's AMDGPU backend source - semantics not yet curated.) |
| v_fmac_f16_t16 | v_fmac_f16_t16 | VOP2 | AMDGPU VOP2 vector instruction operating on f16 data. (Format and name extracted from LLVM's AMDGPU backend source - semantics not yet curated.) |
| v_fmac_f32 | v_fmac_f32 | VOP2 | Multiply two floating point inputs and accumulate the result into the destination register using fused multiply add. |
| v_fmac_f64 | v_fmac_f64 | VOP2 | Multiply two floating point inputs and accumulate the result into the destination register using fused multiply add. |
| v_fmac_legacy_f32 | v_fmac_legacy_f32 | VOP2 | Multiply two single-precision values and accumulate the result with the destination. Follows DX9 rules where 0.0 times anything produces 0.0. |
| v_fmamk_f16 | v_fmamk_f16 | VOP2 | Multiply a half-precision float input with a literal constant and add a second half-precision float input using fused multiply add, and store the… |
| v_fmamk_f16_fake16 | v_fmamk_f16_fake16 | VOP2 | AMDGPU VOP2 vector instruction operating on f16 data. (Format and name extracted from LLVM's AMDGPU backend source - semantics not yet curated.) |
| v_fmamk_f16_t16 | v_fmamk_f16_t16 | VOP2 | AMDGPU VOP2 vector instruction operating on f16 data. (Format and name extracted from LLVM's AMDGPU backend source - semantics not yet curated.) |
| v_fmamk_f32 | v_fmamk_f32 | VOP2 | Multiply a single-precision float input with a literal constant and add a second single-precision float input using fused multiply add, and store the… |
| v_fmamk_f64 | v_fmamk_f64 | VOP2 | AMDGPU VOP2 vector instruction operating on f64 data. (Format and name extracted from LLVM's AMDGPU backend source - semantics not yet curated.) |
| v_fract_f16 | v_fract_f16 | VOP1 | Compute the fractional portion of a half-precision float input and store the result in floating point format into a vector register. |
| v_fract_f32 | v_fract_f32 | VOP1 | Compute the fractional portion of a single-precision float input and store the result in floating point format into a vector register. |
| v_fract_f64 | v_fract_f64 | VOP1 | Compute the fractional portion of a double-precision float input and store the result in floating point format into a vector register. |
| v_frexp_exp_i16_f16 | v_frexp_exp_i16_f16 | VOP1 | Extract the exponent of a half-precision float input and store the result as a signed 16-bit integer into a vector register. |
| v_frexp_exp_i32_f32 | v_frexp_exp_i32_f32 | VOP1 | Extract the exponent of a single-precision float input and store the result as a signed 32-bit integer into a vector register. |
| v_frexp_exp_i32_f64 | v_frexp_exp_i32_f64 | VOP1 | Extract the exponent of a double-precision float input and store the result as a signed 32-bit integer into a vector register. |
| v_frexp_mant_f16 | v_frexp_mant_f16 | VOP1 | Extract the binary significand, or mantissa, of a half-precision float input and store the result as a half- precision float into a vector register. |
| v_frexp_mant_f32 | v_frexp_mant_f32 | VOP1 | Extract the binary significand, or mantissa, of a single-precision float input and store the result as a single- precision float into a vector… |
| v_frexp_mant_f64 | v_frexp_mant_f64 | VOP1 | Extract the binary significand, or mantissa, of a double-precision float input and store the result as a double- precision float into a vector… |
| v_interp_mov_f32 | v_interp_mov_f32 | VOP3 | Given an attribute specifier and a parameter ID (P0, P10 or P20), load one of the parameter values from the local data share into a vector register. |
| v_interp_p1_f32 | v_interp_p1_f32 | VOP3 | Given the I coordinate in a vector register and an attribute specifier, load parameter data from the local data share, compute the first part of… |
| v_interp_p1ll_f16 | v_interp_p1ll_f16 | VOP3 | Given a single-precision float I coordinate in a vector register and an attribute specifier, load two half-precision float parameter values from the… |
| v_interp_p1lv_f16 | v_interp_p1lv_f16 | VOP3 | Given a single-precision float I coordinate in a vector register, a half-precision float P0 value in another vector register, and an attribute… |
| v_interp_p2_f16 | v_interp_p2_f16 | VOP3 | Given a single-precision float J coordinate in a vector register, an attribute specifier and the result of a prior V_INTERP_P1_F32 in another vector… |
| v_interp_p2_f16_opsel | v_interp_p2_f16_opsel | VOP3 | AMDGPU VOP3 vector instruction operating on f16 data. (Format and name extracted from LLVM's AMDGPU backend source - semantics not yet curated.) |
| v_interp_p2_legacy_f16 | v_interp_p2_legacy_f16 | VOP3 | Half-precision interpolation. |
| v_ldexp_f16 | v_ldexp_f16 | VOP2 | Multiply the first input, a floating point value, by an integral power of 2 specified in the second input, a signed integer value, and store the… |
| v_ldexp_f16_fake16 | v_ldexp_f16_fake16 | VOP2 | AMDGPU VOP2 vector instruction operating on f16 data. (Format and name extracted from LLVM's AMDGPU backend source - semantics not yet curated.) |
| v_ldexp_f16_t16 | v_ldexp_f16_t16 | VOP2 | AMDGPU VOP2 vector instruction operating on f16 data. (Format and name extracted from LLVM's AMDGPU backend source - semantics not yet curated.) |
| v_ldexp_f32 | v_ldexp_f32 | VOP2 | Multiply the first input, a floating point value, by an integral power of 2 specified in the second input, a signed integer value, and store the… |
| v_ldexp_f64 | v_ldexp_f64 | VOP3 | Multiply the first input, a floating point value, by an integral power of 2 specified in the second input, a signed integer value, and store the… |
| v_lerp_u8 | v_lerp_u8 | VOP3 | Average two 4-D vectors stored as packed bytes in the first two inputs with rounding control provided by the third input, then store the result into… |
| v_log_bf16 | v_log_bf16 | VOP1 | AMDGPU VOP1 vector instruction. (Format and name extracted from LLVM's AMDGPU backend source - semantics not yet curated.) |
| v_log_f16 | v_log_f16 | VOP1 | Calculate the base 2 logarithm of the half-precision float input and store the result into a vector register. |
| v_log_f32 | v_log_f32 | VOP1 | Calculate the base 2 logarithm of the single-precision float input and store the result into a vector register. |
| v_log_legacy_f32 | v_log_legacy_f32 | VOP1 | AMDGPU VOP1 vector instruction operating on f32 data. (Format and name extracted from LLVM's AMDGPU backend source - semantics not yet curated.) |
| v_lshl_add_u32 | v_lshl_add_u32 | VOP3 | Given a shift count in the second input, calculate the logical shift left of the first input, then add the third input to the intermediate result… |
| v_lshl_add_u64 | v_lshl_add_u64 | VOP3 | Given a shift count in the second input, calculate the logical shift left of the first input, then add the third input to the intermediate result… |
| v_lshl_b32 | v_lshl_b32 | VOP2 | AMDGPU VOP2 vector instruction operating on b32 data. (Format and name extracted from LLVM's AMDGPU backend source - semantics not yet curated.) |
| v_lshl_b64 | v_lshl_b64 | VOP3 | AMDGPU VOP3 vector instruction operating on b64 data. (Format and name extracted from LLVM's AMDGPU backend source - semantics not yet curated.) |
| v_lshl_or_b32 | v_lshl_or_b32 | VOP3 | Given a shift count in the second input, calculate the logical shift left of the first input, then calculate the bitwise OR of the intermediate… |
| v_lshlrev_b16 | v_lshlrev_b16 | VOP2 | Given a shift count in the first vector input, calculate the logical shift left of the second vector input and store the result into a vector… |
| v_lshlrev_b32 | v_lshlrev_b32 | VOP2 | Given a shift count in the first vector input, calculate the logical shift left of the second vector input and store the result into a vector… |
| v_lshlrev_b64 | v_lshlrev_b64 | VOP2 | Given a shift count in the first vector input, calculate the logical shift left of the second vector input and store the result into a vector… |
| v_lshlrev_b64_pseudo | v_lshlrev_b64_pseudo | VOP2 | AMDGPU VOP2 vector instruction operating on b64 data. (Format and name extracted from LLVM's AMDGPU backend source - semantics not yet curated.) |
| v_lshr_b32 | v_lshr_b32 | VOP2 | AMDGPU VOP2 vector instruction operating on b32 data. (Format and name extracted from LLVM's AMDGPU backend source - semantics not yet curated.) |
| v_lshr_b64 | v_lshr_b64 | VOP3 | AMDGPU VOP3 vector instruction operating on b64 data. (Format and name extracted from LLVM's AMDGPU backend source - semantics not yet curated.) |
| v_lshrrev_b16 | v_lshrrev_b16 | VOP2 | Given a shift count in the first vector input, calculate the logical shift right of the second vector input and store the result into a vector… |
| v_lshrrev_b32 | v_lshrrev_b32 | VOP2 | Given a shift count in the first vector input, calculate the logical shift right of the second vector input and store the result into a vector… |
| v_lshrrev_b64 | v_lshrrev_b64 | VOP3 | Given a shift count in the first vector input, calculate the logical shift right of the second vector input and store the result into a vector… |
| v_mac_f16 | v_mac_f16 | VOP2 | Multiply two floating point inputs and accumulate the result into the destination register. Implements IEEE rules and non-standard rule for OPSEL. |
| v_mac_f32 | v_mac_f32 | VOP2 | Multiply two floating point inputs and accumulate the result into the destination register. |
| v_mac_legacy_f32 | v_mac_legacy_f32 | VOP2 | Multiply and add single-precision values, accumulate with destination. Follows DX9 rules where 0.0 times anything produces 0.0. |
| v_mad_co_i64_i32 | v_mad_co_i64_i32 | VOP3 | Multiply two signed integer inputs, add a third signed integer input, store the result into a 64-bit vector register and store the overflow/carryout… |
| v_mad_co_u64_u32 | v_mad_co_u64_u32 | VOP3 | Multiply two unsigned integer inputs, add a third unsigned integer input, store the result into a 64-bit vector register and store the… |
| v_mad_f16 | v_mad_f16 | VOP3 | Multiply two half-precision float inputs and add a third input, and store the result into a vector register. |
| v_mad_f16_gfx9 | v_mad_f16_gfx9 | VOP3 | AMDGPU VOP3 vector instruction operating on f16 data. (Format and name extracted from LLVM's AMDGPU backend source - semantics not yet curated.) |
| v_mad_f32 | v_mad_f32 | VOP3 | Multiply two single-precision float inputs and add a third input, and store the result into a vector register. |
| v_mad_i16 | v_mad_i16 | VOP3 | Multiply two signed 16-bit integer inputs, add a signed 16-bit integer value from a third input, and store the result into a vector register. |
| v_mad_i16_gfx9 | v_mad_i16_gfx9 | VOP3 | AMDGPU VOP3 vector instruction operating on i16 data. (Format and name extracted from LLVM's AMDGPU backend source - semantics not yet curated.) |
| v_mad_i32_i16 | v_mad_i32_i16 | VOP3 | Multiply two signed 16-bit integer inputs in the signed 32-bit integer domain, add a signed 32-bit integer value from a third input, and store the… |
| v_mad_i32_i24 | v_mad_i32_i24 | VOP3 | Multiply two signed 24-bit integer inputs in the signed 32-bit integer domain, add a signed 32-bit integer value from a third input, and store the… |
| v_mad_i64_i32 | v_mad_i64_i32 | VOP3 | Multiply two signed integer inputs, add a third signed integer input, store the result into a 64-bit vector register and store the overflow/carryout… |
| v_mad_legacy_f16 | v_mad_legacy_f16 | VOP3 | Multiply add of FP16 values. Implements IEEE rules and non-standard rule for OPSEL. |
| v_mad_legacy_f32 | v_mad_legacy_f32 | VOP3 | Multiply and add single-precision values. Follows DX9 rules where 0.0 times anything produces 0.0. |
| v_mad_legacy_i16 | v_mad_legacy_i16 | VOP3 | Multiply add of signed short values. Has non-standard rule for OPSEL. |
| v_mad_legacy_u16 | v_mad_legacy_u16 | VOP3 | Multiply add of unsigned short values. Has non-standard rule for OPSEL. |
| v_mad_nc_i64_i32 | v_mad_nc_i64_i32 | VOP3 | AMDGPU VOP3 vector instruction operating on i32/i64 data. (Format and name extracted from LLVM's AMDGPU backend source - semantics not yet curated.) |
| v_mad_nc_u64_u32 | v_mad_nc_u64_u32 | VOP3 | AMDGPU VOP3 vector instruction operating on u32/u64 data. (Format and name extracted from LLVM's AMDGPU backend source - semantics not yet curated.) |
| v_mad_u16 | v_mad_u16 | VOP3 | Multiply two unsigned 16-bit integer inputs, add an unsigned 16-bit integer value from a third input, and store the result into a vector register. |
| v_mad_u16_gfx9 | v_mad_u16_gfx9 | VOP3 | AMDGPU VOP3 vector instruction operating on u16 data. (Format and name extracted from LLVM's AMDGPU backend source - semantics not yet curated.) |
| v_mad_u32 | v_mad_u32 | VOP3 | AMDGPU VOP3 vector instruction operating on u32 data. (Format and name extracted from LLVM's AMDGPU backend source - semantics not yet curated.) |
| v_mad_u32_u16 | v_mad_u32_u16 | VOP3 | Multiply two unsigned 16-bit integer inputs in the unsigned 32-bit integer domain, add an unsigned 32-bit integer value from a third input, and store… |
| v_mad_u32_u24 | v_mad_u32_u24 | VOP3 | Multiply two unsigned 24-bit integer inputs in the unsigned 32-bit integer domain, add a unsigned 32-bit integer value from a third input, and store… |
| v_mad_u64_u32 | v_mad_u64_u32 | VOP3 | Multiply two unsigned integer inputs, add a third unsigned integer input, store the result into a 64-bit vector register and store the… |
| v_madak_f16 | v_madak_f16 | VOP2 | Multiply two floating point inputs and add a literal constant, and store the result into a vector register. Implements IEEE rules. |
| v_madak_f32 | v_madak_f32 | VOP2 | Multiply two floating point inputs and add a literal constant, and store the result into a vector register. |
| v_madmk_f16 | v_madmk_f16 | VOP2 | Multiply a floating point input with a literal constant and add a second floating point input, and store the result into a vector register. |
| v_madmk_f32 | v_madmk_f32 | VOP2 | Multiply a floating point input with a literal constant and add a second floating point input, and store the result into a vector register. |
| v_max3_f16 | v_max3_f16 | VOP3 | Select the maximum of three half-precision float inputs and store the selected value into a vector register. |
| v_max3_f32 | v_max3_f32 | VOP3 | Select the maximum of three single-precision float inputs and store the selected value into a vector register. |
| v_max3_i16 | v_max3_i16 | VOP3 | Select the maximum of three signed 16-bit integer inputs and store the selected value into a vector register. |
| v_max3_i32 | v_max3_i32 | VOP3 | Select the maximum of three signed 32-bit integer inputs and store the selected value into a vector register. |
| v_max3_num_f16 | v_max3_num_f16 | VOP3 | Select the IEEE maximumNumber() of three half-precision float inputs and store the selected value into a vector register. |
| v_max3_num_f32 | v_max3_num_f32 | VOP3 | Select the IEEE maximumNumber() of three single-precision float inputs and store the selected value into a vector register. |
| v_max3_u16 | v_max3_u16 | VOP3 | Select the maximum of three unsigned 16-bit integer inputs and store the selected value into a vector register. |
| v_max3_u32 | v_max3_u32 | VOP3 | Select the maximum of three unsigned 32-bit integer inputs and store the selected value into a vector register. |