Bit-Field Extract Bit Manipulation
Extract a contiguous bit field from an operand, zero- or sign-extending the result.
Vendor-Neutral Definition
d = (a >> pos) & ((1 << len) - 1), then zero- or sign-extended per the operand's signedness.
⚠️ Cross-vendor mappings describe semantic relationships and are not guaranteed one-to-one compiler
translations.
equivalent with restrictions
Both extract a bit field given a start position and length; AMDGPU requires selecting the correctly-signed/scalar-or-vector instruction rather than one generic mnemonic.
| Property | NVIDIA PTX | AMDGPU |
|---|---|---|
| Instruction | bfe | v_bfe_u32, v_bfe_i32, s_bfe_u32 |
| ISA Layer | Virtual | Native |
| Data Types | - | i32, u32 |
| Version / Target Introduced | PTX ISA 2.0 | gfx1100, gfx1100, gfx1100 |
Important Differences
- PTX's bfe is one family covering s32/u32/s64/u64 via a type modifier; AMDGPU exposes separate zero-extending (v_bfe_u32) and sign-extending (v_bfe_i32) instructions, each in scalar and vector forms.
- AMDGPU packs the start position and field length into a single SRC1 operand (offset in bits [4:0], width in bits [22:16]) rather than PTX's two separate operands.
Source Evidence
- Parallel Thread Execution ISA ↗ - NVIDIA Corporation
- "AMD Instinct MI300" Instruction Set Architecture: Reference Guide ↗ - Advanced Micro Devices, Inc.
Verification method: documentation