Cross-ISA CPU Comparison

23 vendor-neutral operations, each showing how x86, ARM, RISC-V, PowerISA express it. Where an architecture has no instruction for an operation, that is shown explicitly with the reason: those gaps are often the most revealing part of the comparison.

These mappings describe semantic correspondence, not drop-in equivalence. Flag behavior, trap behavior, memory ordering, and operand widths frequently differ; follow the instruction links for the exact per-architecture semantics.
Operation x86ARMRISC-VPowerISA
Add With Carry adc adc, adcs none addc, adde
Atomic Compare and Swap cmpxchg cas, casal LR.W, SC.W, AMOCAS.W lwarx, stwcx., ldarx idiom
Atomic Fetch and Add xadd ldadd AMOADD.W, AMOADD.D lwarx, stwcx. idiom
Breakpoint Trap int3 brk EBREAK trap, tw, twi
Byte Swap (Endianness Reversal) bswap rev, rev16, rev32 REV8 lwbrx, stwbrx idiom
Cache Line Flush clflush, clflushopt dc CBO.FLUSH, CBO.CLEAN dcbf
Cache Prefetch Hint prefetcht0, prefetchnta prfm PREFETCH.R, PREFETCH.W dcbt, dcbtst
Compare and Branch cmp, je idiom cbz, cbnz BEQ, BNE cmp, cmpi, bc idiom
Conditional Select (Branchless Move) cmovcc, cmovz, cmovg csel, csinc CZERO.EQZ, CZERO.NEZ isel
Count Leading Zeros lzcnt, bsr clz CLZ cntlzd, cntlzw
Count Trailing Zeros tzcnt, bsf rbit, clz idiom CTZ cnttzd, cnttzw
Floating-Point Square Root sqrtsd, sqrtss fsqrt FSQRT.D, FSQRT.S fsqrt, fsqrts
Fused Multiply-Add vfmadd132ss, vfmadd213ss fmadd, fmla FMADD.D, FMADD.S fmadd
Integer Addition add add ADD, ADDI add, addi
Integer Divide idiv, div sdiv, udiv DIV, DIVU divd, divw
Integer Multiply imul, mul mul, madd MUL, MULH mulld, mullw
Load-Acquire none ldar, ldaxr LR.W, LR.D lwz, lwsync idiom
Memory Barrier / Fence mfence, lfence, sfence dmb, dsb FENCE sync, lwsync, eieio
No Operation nop nop NOP nop, ori
Population Count popcnt cnt idiom CPOP popcntd, popcntw, popcntb
Rotate Left rol ror idiom ROL, ROR rldicl, rlwinm
Sign Extend Byte movsx sxtb SEXT.B extsb
System Call syscall, int svc ECALL sc