Breakpoint Trap

Raise a debug exception so a debugger can take control.

System

Semantics

Generates a synchronous debug/breakpoint exception. This is the instruction a debugger patches into code to set a software breakpoint.

Architecture Instructions Expressed as How this architecture does it
x86 one instruction A deliberately one-byte encoding (0xCC) so a debugger can overwrite any instruction's first byte in place.
ARM one instruction BRK takes a 16-bit immediate that debuggers use to tag which breakpoint fired.
RISC-V one instruction The compressed C.EBREAK form exists so a breakpoint can be patched over a 16-bit instruction.
PowerISA one instruction The trap instructions are conditional: tw traps when a comparison holds, and the unconditional trap is the canonical debugger form.

Other operations

Add With Carry Atomic Compare and Swap Atomic Exchange Atomic Fetch and Add Byte Swap (Endianness Reversal) CPU Feature Detection Cache Line Flush Cache Prefetch Hint Compare and Branch Conditional Select (Branchless Move) Count Leading Zeros Count Trailing Zeros Enable and Disable Interrupts Floating-Point Compare Floating-Point Square Root Function Call and Return Fused Multiply-Add Indirect Branch Instruction Cache Synchronisation Integer Addition Integer Divide Integer Multiply Integer and Floating-Point Conversion Load and Store Load-Acquire Load-Linked / Store-Conditional Logical and Arithmetic Shift Materialise a Large Constant Memory Barrier / Fence Multiply High No Operation PC-Relative Address Population Count Read Cycle Counter Return From Exception Rotate Left Sign Extend Byte Speculation Barrier Spin-Wait Hint Stack Push and Pop System Call