Breakpoint Trap

Raise a debug exception so a debugger can take control.

System

Semantics

Generates a synchronous debug/breakpoint exception. This is the instruction a debugger patches into code to set a software breakpoint.

Architecture	Instructions	Expressed as	How this architecture does it
x86	int3 Base	one instruction	A deliberately one-byte encoding (0xCC) so a debugger can overwrite any instruction's first byte in place.
ARM	brk Base	one instruction	BRK takes a 16-bit immediate that debuggers use to tag which breakpoint fired.
RISC-V	EBREAK RV32I	one instruction	The compressed C.EBREAK form exists so a breakpoint can be patched over a 16-bit instruction.
PowerISA	trap Base tw Base twi Base	one instruction	The trap instructions are conditional: tw traps when a comparison holds, and the unconditional trap is the canonical debugger form.

Other operations

Add With Carry Atomic Compare and Swap Atomic Fetch and Add Byte Swap (Endianness Reversal) Cache Line Flush Cache Prefetch Hint Compare and Branch Conditional Select (Branchless Move) Count Leading Zeros Count Trailing Zeros Floating-Point Square Root Fused Multiply-Add Integer Addition Integer Divide Integer Multiply Load-Acquire Memory Barrier / Fence No Operation Population Count Rotate Left Sign Extend Byte System Call