tw

Trap Word

tw TO, RA, RB

Traps if condition (comparison of words) is met.

Encoding

Binary Layout

0:5

6:10

11:15

16:20

21:31

Format X-form

Opcode 0x7C000008

Extension Base

Operands

TO
Options
RA
Src A
RB
Src B

Example

tw 4, r4, r5

Registers Altered

CR0, CR1, CR6

Across architectures

Breakpoint Trap : how x86, ARM, RISC-V, and PowerISA each do this.

Reference

View in PowerISA v3.1C Specification ↗ OPF Power ISA v3.1C

Description

Compares the 32-bit signed values in RA and RB according to the trap condition bits in TO. If the condition is true, a program interrupt (trap) is generated; otherwise execution continues. The TO field encodes up to five independent comparison conditions (less-than, greater-than, equal, unsigned less-than, unsigned greater-than).

Operation

if (TO[0] & (RA <s RB)) | (TO[1] & (RA >s RB)) | (TO[2] & (RA = RB)) | (TO[3] & (RA <u RB)) | (TO[4] & (RA >u RB)) then
  Trap_Exception ← 1
else
  Trap_Exception ← 0

Programming Note

Generates a program exception (System Call or Trap type) when the trap condition is true. The condition codes in TO select which comparisons trigger the trap: bit 0 = LT, bit 1 = GT, bit 2 = EQ, bit 3 = LU (unsigned), bit 4 = GU (unsigned). TO=31 (all bits set) always traps.

tw