vpmsumw

Vector Polynomial Multiply-Sum Word

vpmsumw vD, vA, vB

Performs a polynomial multiply-sum operation on word elements of two vector registers and stores the result in another vector register.

Encoding

Binary Layout

0:5

6:10

11:15

16:20

1160

21:31

Format VX-form

Opcode 0x10000488

Extension Vector Crypto

Operands

vD
Target
vA
Src A
vB
Src B
VRT
Target Vector Register
VRA
Source Vector Register
VRB
Source Vector Register

Example

vpmsumw vd, va, vb

Registers Altered

MSR

Reference

View in PowerISA v3.1C Specification ↗ OPF Power ISA v3.1C

Description

Performs GF(2) polynomial multiplication on pairs of 32-bit word elements from vA and vB, accumulating the results into vD. This instruction is part of the Vector Crypto extension and is essential for cryptographic operations such as CRC and GHASH computation. No condition registers or exception flags are modified.

Operation

for i in 0 to 1:
  prod ← PolyMultiply_GF2(vA[32*i:32*i+31], vB[32*i:32*i+31])
  vD[64*i:64*i+63] ← vD[64*i:64*i+63] XOR prod

Programming Note

The vpmsumw instruction is used for polynomial multiplication of word elements in vector registers. Ensure that the Vector Facility is enabled by checking and setting the VEC bit in the MSR register. This instruction operates on 128-bit vectors, processing four 32-bit words each. Be cautious with alignment; input vectors must be properly aligned to avoid undefined behavior. The result is a 64-bit word for each pair of input words, XORed together and stored in the destination vector. Exception conditions include invalid use of registers or disabled Vector Facility.