vpmsumw

Vector Polynomial Multiply-Sum Word

vpmsumw vD, vA, vB

Performs a polynomial multiply-sum operation on word elements of two vector registers and stores the result in another vector register.

Details

The vpmsumw instruction performs a binary polynomial multiplication of each pair of corresponding word elements from VSR[VRA+32] and VSR[VRB+32], then XORs the results to produce the final output.

Pseudocode Operation

if MSR.VEC=0 then
    Vector_Unavailable()
do i = 0 to 3
    prod[i].bit[0:62] ←0
    srcA ←VSR[VRA+32].word[i]
    srcB ←VSR[VRB+32].word[i]
    do j = 0 to 31
        do k = 0 to j
            gbit ←srcA.bit[k] & srcB.bit[j-k]
            prod[i].bit[j] ←prod[i].bit[j] ⊕gbit
        end
    end
    do j = 32 to 62
        do k = j-31 to 31
            gbit ←(srcA.bit[k] & srcB.bit[j-k])
            prod[i].bit[j] ←prod[i].bit[j] ⊕gbit
        end
    end
end
VSR[VRT+32].dword[0] ←0b0 || (prod[0] ⊕prod[1])
VSR[VRT+32].dword[1] ←0b0 || (prod[2] ⊕prod[3])

Programming Note

The vpmsumw instruction is used for polynomial multiplication of word elements in vector registers. Ensure that the Vector Facility is enabled by checking and setting the VEC bit in the MSR register. This instruction operates on 128-bit vectors, processing four 32-bit words each. Be cautious with alignment; input vectors must be properly aligned to avoid undefined behavior. The result is a 64-bit word for each pair of input words, XORed together and stored in the destination vector. Exception conditions include invalid use of registers or disabled Vector Facility.

Example

vpmsumw vd, va, vb

Encoding

Binary Layout
4
0
vD
6
vA
11
vB
16
1160
 
Format VX-form
Opcode 0x10000488
Extension Vector Crypto
Registers Altered MSR

Operands

  • vD
    Target
  • vA
    Src A
  • vB
    Src B
  • VRT
    Target Vector Register
  • VRA
    Source Vector Register
  • VRB
    Source Vector Register