xxgenpcvbm

VSX Vector Generate Permute Control Vector from Byte Mask

xxgenpcvbm XT, XB, IMM

Generates a permute control vector based on the byte mask in VSR[VRB+32].

Details

The xxgenpcvbm instruction generates a permute control vector (PCV) based on the byte mask in VSR[VRB+32] and stores it in VSR[XT]. The operation depends on the value of IMM.

Pseudocode Operation

if MSR.VSX=0 then VSX_Unavailable()
XT ←32×TX+T
if IMM=0b00000 then do // Big-Endian expansion
    j ←0
    for i = 0 to 15 do
        if VSR[VRB+32].byte[i].bit[0]=1 then do
            VSR[XT].byte[i] ←j
            j ←j + 1
        end else
            VSR[XT].byte[i] ←i + 0x10
    end
end else if IMM=0b00001 then do // Big-Endian compression
    j ←0
    for i = 0 to 15 do
        if VSR[VRB+32].byte[i].bit[0]=1 then do
            VSR[XT].byte[j] = i
            j = j + 1
        end
    end
    for i = j to 15 do
        VSR[XT].byte[i] = 0xUU
    end
end else if IMM=0b00010 then do // Little-Endian expansion
    j ←0
    for i = 0 to 15 do
        if VSR[VRB+32].byte[15-i].bit[0]=1 then do
            VSR[XT].byte[15-i] ←j
            j ←j + 1
        end else
            VSR[XT].byte[15-i] ←i + 0x10
    end
end else if IMM=0b00011 then do // Little-Endian compression
    j ←0
    for i = 0 to 15 do
        if VSR[VRB+32].byte[15-i].bit[0]=1 then do
            VSR[XT].byte[15-j] ←i
            j ←j + 1
        end
    end
end

Programming Note

The xxgenpcvbm instruction is used to generate a permute control vector based on a byte mask. Ensure the VSX facility is enabled by checking and setting the MSR.VSX bit. The operation mode (expansion or compression) and endianness (big or little) are determined by the IMM field. Be cautious with alignment as VSR registers must be properly aligned for operations.

Example

xxgenpcvbm vs1, vs3, 1

Encoding

Binary Layout
60
0
XT
6
IMM
11
XB
16
916
21
 
Format XX2-form
Opcode 0xF0000394
Extension VSX
Registers Altered MSR

Operands

  • XT
    Target
  • XB
    Source
  • IMM
    Mask
  • VRB
    Source Vector Register
  • vPCV
    Target Vector Register
  • vMASK
    Source Vector Register containing the mask byte
  • IMM8
    Immediate value specifying the control vector type