trap

Trap (Pseudo)

trap

Unconditional trap. Forces an exception. (Encoded as tw 31, 0, 0).

Encoding

Binary Layout

3

0:5

11111

6:10

00000

11:15

00000

16:20

4

21:30

/

31

 

Format Pseudo

Opcode 0x0FE00008

Extension Base

Operands

Registers Altered

MSR, SRR0, SRR1

Related

Across architectures

Breakpoint Trap : how x86, ARM, RISC-V, and PowerISA each do this.

More in Base

Reference

View in PowerISA v3.1C Specification ↗ OPF Power ISA v3.1C

Description

Trap. Extended mnemonic for TW (tw 31,0,0). Unconditionally traps, transferring control to the system trap handler.

Operation

Trap()

Programming Note

Generates a program exception (System Call or Trap type) when the trap condition is true. The condition codes in TO select which comparisons trigger the trap: bit 0 = LT, bit 1 = GT, bit 2 = EQ, bit 3 = LU (unsigned), bit 4 = GU (unsigned). TO=31 (all bits set) always traps.