bclr

Branch Conditional to Link Register

bclr BO,BI,BH

Branches to the address in the Link Register (LR) if the condition is met. Used for function returns.

Encoding

Binary Layout

0:5

6:10

11:15

000

16:20

21:30

Format XL-form

Opcode 0x4C000020

Extension Base

Operands

BO
Branch Options
BI
CR Bit Index
BH
Hint bits
LK
Link Register Update field

Example

bclr 20, 0

// Unconditional return (blr).

Registers Altered

CTR, LR

Across architectures

Function Call and Return : how x86, ARM, RISC-V, and PowerISA each do this.

Reference

View in PowerISA v3.1C Specification ↗ OPF Power ISA v3.1C

Description

Branches to the address in the Link Register (LR) if the condition specified by BO and BI is satisfied. The CTR is decremented if BO[2]=0. If LK=1, the return address (CIA + 4) is saved in LR, enabling exception-safe subroutine returns. The BH field provides a branch prediction hint to the processor.

Operation

ctr_ok ← (BO[2] = 1) | (CTR ≠ 0 ⊕ BO[3])
if BO[2] = 0 then CTR ← CTR - 1
cr_ok ← (BO[0] = 1) | (CR[BI] = BO[1])
if ctr_ok & cr_ok then NIA ← LR[0:61] || 0b00
if LK = 1 then LR ← CIA + 4

Extended Mnemonics

Extended Mnemonic	Equivalent Instruction
bcctr	bcctr BO,BI,BH
bltctr	bcctr 12,0,0
bnectr	bcctr 4,10,0
bclr	bclr BO,BI,BH
bltlr	bclr 12,0,0
bnelr	bclr 4,10,0
bdnzlr	bclr 16,0,0
bcctr	bcctr BO,BI,BH (LK=0)
bcctrl	bcctr BO,BI,BH (LK=1)
bclr 4,6	bclr 4,6,0
bnelr cr2	bclr 4,10,0

Programming Note

bclr, bclrl, bcctr, and bcctrl each serve as both a basic and an extended mnemonic. The Assembler will recognize a bclr, bclrl, bcctr, or bcctrl mnemonic with three operands as the basic form, and a bclr, bclrl, bcctr, or bcctrl mnemonic with two operands as the extended form. In the extended form the BH operand is omitted and assumed to be 0b00.