bcdcfsq.

Decimal Convert from Signed Quadword

bcdcfsq. vD, vB, PS

Converts a signed quadword integer to packed decimal format and updates the condition register.

Encoding

Binary Layout

0:5

6:10

11:15

16:20

193

21:31

Format VX-form

Opcode 0x10020581

Extension Vector BCD

Operands

vD
Target
vB
Source
PS
Sign
VRT
Target Vector Register
VRB
Source Vector Register

Example

bcdcfsq. vd, vb, 0

Registers Altered

CR0, CR1-CR7, XER, LR, CTR

Reference

View in PowerISA v3.1C Specification ↗ OPF Power ISA v3.1C

Description

The bcdcfsq. instruction converts a signed quadword integer from VSR[VRB+32] to packed decimal format and stores it in VSR[VRT+32]. It also updates the condition register CR6 based on the conversion result.

Operation

if MSR.VEC=0 then
    Vector_Unavailable()

ox_flag ←(EXTS(VSR[VRB+32]) > 1031-1) |
           (EXTS(VSR[VRB+32]) < -(1031-1))
lt_flag ←(EXTS(VSR[VRB+32]) < 0)
gt_flag ←(EXTS(VSR[VRB+32]) > 0)
eq_flag ←(EXTS(VSR[VRB+32]) = 0)

if ox_flag=0 then
   result ←bcd_CONVERT_FROM_SI128(EXTS(VSR[VRB+32]),PS)
else
   result ←0xUUUU_UUUU_UUUU_UUUU_UUUU_UUUU_UUUU_UUUU

VSR[VRT+32] ←ox_flag ? undefined : result

CR.bit[56] ←lt_flag
CR.bit[57] ←gt_flag
CR.bit[58] ←eq_flag
CR.bit[59] ←ox_flag

Programming Note

The bcdcfsq. instruction is used to convert a signed quadword integer to packed decimal format, storing the result in VSR[VRT+32]. It updates CR6 with flags indicating overflow (OX), less than (LT), greater than (GT), and equal (EQ) conditions. Ensure that the Vector Facility is enabled by checking MSR.VEC before using this instruction. Be cautious of overflow conditions, as they result in an undefined value being stored.