vupklsh

Vector Unpack Low Signed Halfword

vupklsh vD, vB

Unpacks low 4 signed halfwords to 4 signed words.

Encoding

Binary Layout

4

0:5

vD

6:10

0

11:15

vB

16:20

718

21:31

 

Format VX-form

Opcode 0x100002CE

Extension VMX (AltiVec)

Operands

• vD
  Target
• vB
  Source

Example

vupklsh vd, vb

Registers Altered

MSR

Related

More in VMX (AltiVec)

Reference

View in PowerISA v3.1C Specification ↗ OPF Power ISA v3.1C

Description

Unpacks the four low-order (rightmost) signed halfwords from vB into four signed words in vD, sign-extending each halfword to 32 bits. This is a VMX instruction that does not modify condition or status registers.

Operation

vD[0:31] ← sign_extend(vB[112:127])
vD[32:63] ← sign_extend(vB[96:111])
vD[64:95] ← sign_extend(vB[80:95])
vD[96:127] ← sign_extend(vB[64:79])

Programming Note

This instruction is used to unpack the low halfwords from a source vector register into a destination vector register, sign-extending each halfword to form words. Ensure that the Vector Facility (MSR.VEC) is enabled before using this instruction; otherwise, a Vector_Unavailable exception will be raised. The operation targets the high 128 bits of the vector registers, so ensure that VRB and VRT are correctly set for the desired vector elements.