ps_mul

Paired Single Multiply

ps_mul FRT, FRA, FRC

Multiplies two paired singles.

Encoding

Binary Layout

60

0:5

FRT

6:10

FRA

11:15

FRC

16:20

25

21:31

 

Format A-form

Opcode 0xF0000019

Extension VMX (AltiVec)

Operands

• FRT
  Target
• FRA
  Src A
• FRC
  Src C

Example

ps_mul f1, f2, f4

Related

More in VMX (AltiVec)

Reference

View in PowerISA v3.1C Specification ↗ OPF Power ISA v3.1C

Description

Multiplies two pairs of single-precision floating-point values element-wise, storing the result in FRT. Each of the two single-precision elements in FRA and FRC is multiplied independently. May set FPSCR status flags if exceptions occur.

Operation

FPR[FRT].upper ← FPR[FRA].upper × FPR[FRC].upper
FPR[FRT].lower ← FPR[FRA].lower × FPR[FRC].lower