mcrfs

Move to Condition Register from FPSCR

mcrfs BF, BFA

Moves a field from the Floating-Point Status and Control Register (FPSCR) to the Condition Register.

Encoding

Binary Layout

63

0:5

BF

6:8

/

9:10

BFA

11:13

/

14:20

64

21:30

/

31

 

Format X-form

Opcode 0xFC000080

Extension Floating-Point

Operands

• BF
  Target CR
• BFA
  Src FPSCR
• CRf
  Condition Register Field
• FPSCRf
  Floating-Point Status and Control Register Field

Example

mcrfs cr0, cr1

Registers Altered

CR0, FPSCR

Related

More in Floating-Point

Reference

View in PowerISA v3.1C Specification ↗ OPF Power ISA v3.1C

Description

Moves a 4-bit field from the Floating-Point Status and Control Register (FPSCR) into a 4-bit field of the Condition Register (CR). The source field is specified by BFA and the destination field by BF. The corresponding FPSCR field is cleared after the move, and no other status fields are affected.

Operation

CR[4*BF:4*BF+3] ← FPSCR[4*BFA:4*BFA+3]
FPSCR[4*BFA:4*BFA+3] ← 0

Programming Note

The mcrfs instruction is commonly used to transfer floating-point status and control information from the FPSCR to a general-purpose register. Ensure that the destination register (FRT) is properly aligned for optimal performance. This instruction operates at user privilege level, but accessing certain bits may require higher privileges depending on system configuration. Be cautious of potential exceptions if the FPSCR contains invalid or unexpected values.