mffs.

Move From FPSCR (Record)

mffs. FRT

Moves the contents of the Floating-Point Status and Control Register (FPSCR) into a floating-point register.

Encoding

Binary Layout

63

0:5

FRT

6:10

/

11:15

/

16:20

583

21:30

Rc

31

 

Format X-form

Opcode 0xFC00048E

Extension Floating-Point

Operands

• FRT
  Target

Example

mffs f1

Registers Altered

FPSCR, CR1, (if, Rc=1), CR0

Related

More in Floating-Point

Reference

View in PowerISA v3.1C Specification ↗ OPF Power ISA v3.1C

Description

Moves the contents of the Floating-Point Status and Control Register (FPSCR) into floating-point register FRT. If Rc=1 (mffs.), the instruction updates CR1 based on the moved FPSCR value. This is a privileged instruction that does not alter FPSCR itself.

Operation

FRT ← FPSCR
if Rc = 1 then
  CR1 ← (FRT[0:3])

Extended Mnemonics

Extended Mnemonic	Equivalent Instruction

Programming Note

When Rc=1, CR1 is set from the FPSCR[FX, FEX, VX, OX] bits immediately after the operation completes.