fnmadd

Floating Negative Multiply-Add

fnmadd FRT,FRA,FRC,FRB

Performs a floating-point negative multiply-add operation.

Encoding

Binary Layout

63

0:5

FRT

6:10

FRA

11:15

FRB

16:20

FRC

21:25

31

26:30

/

31

 

Format A-form

Opcode 0xFC00003E

Extension Floating-Point

Operands

• FRT
  Target
• FRA
  A
• FRC
  C
• FRB
  B

Example

fnmadd f1, f2, f4, f3

Registers Altered

FPSCR, CR1

Related

More in Floating-Point

Reference

View in PowerISA v3.1C Specification ↗ OPF Power ISA v3.1C

Description

The operation FRT ←- ( [(FRA)×(FRC)] + (FRB) ) is performed. The result is negated and placed into register FRT.

Operation

FRT ←- ( [(FRA)×(FRC)] + (FRB) )
if 'fnmadd.' then
    update CR1 and FPSCR fields

Programming Note

The fnmadd instruction is useful for performing a negated multiply-add operation on floating-point numbers. Ensure that the input registers FRA, FRC, and FRB are correctly aligned and contain valid floating-point values to avoid exceptions. If using the 'fnmadd.' form, be aware that it updates CR1 and FPSCR, which can affect subsequent conditional operations or exception handling.