fmsub

Floating Multiply-Subtract

fmsub FRT, FRA, FRC, FRB

Multiplies two floating-point values and subtracts a third.

Encoding

Binary Layout

63

0:5

FRT

6:10

FRA

11:15

FRB

16:20

FRC

21:25

28

26:30

/

31

 

Format A-form

Opcode 0xFC000038

Extension Floating-Point

Operands

• FRT
  Target
• FRA
  A
• FRC
  C
• FRB
  B

Example

fmsub f1, f2, f4, f3

Registers Altered

FPSCR

Related

More in Floating-Point

Reference

View in PowerISA v3.1C Specification ↗ OPF Power ISA v3.1C

Description

Performs a fused multiply-subtract operation: (FRA × FRC) - FRB in extended precision, then rounds to double-precision and places the result in FRT. FPSCR exception flags and FPRF are updated; this provides higher precision than separate multiply and subtract instructions.

Operation

FRT ← Round((FRA × FRC) - FRB)
FPSCR[FPRF, XX, ZX, UX, OX, VXISI] ← updated based on operation

Programming Note

The fmsub instruction is useful for performing fused multiply-subtract operations, which can help reduce rounding errors. Ensure that the input registers are properly aligned and contain valid floating-point numbers to avoid exceptions. This operation requires FPSCR to manage precision and exception flags.