fcfid

Floating Convert with round Signed Doubleword to Double-Precision format

fcfid FRT,FRB

Converts a signed doubleword integer to a double-precision floating-point number.

Encoding

Binary Layout

63

0:5

FRT

6:10

0

11:15

FRB

16:20

846

21:30

/

31

 

Format X-form

Opcode 0xFC00069C

Extension Floating-Point

Operands

• FRT
  Target
• FRB
  Source

Example

fcfid f1, f3

Registers Altered

FPSCR, CR1 (if Rc=1)

Related

Across architectures

Integer and Floating-Point Conversion : how x86, ARM, RISC-V, and PowerISA each do this.

More in Floating-Point

Reference

View in PowerISA v3.1C Specification ↗ OPF Power ISA v3.1C

Description

The 64-bit signed fixed-point operand in register FRB is converted to an infinitely precise floating-point integer. The result of the conversion is rounded to double-precision, using the rounding mode specified by RN, and placed into register FRT.

Operation

if 'fcfid' then
    FRT <- (FRB) converted to double-precision floating-point integer
    round result using RN
    if Rc=1 then update CR1

Programming Note

Converting a signed integer word to double-precision floating-point can be accomplished by loading the word from storage using Load Float Word Algebraic Indexed and then using fcfid.