drrnd

Decimal Floating-Point Reround

drrnd FRT,FRA,FRB,RMC

Rounds a decimal floating-point value to the specified number of significant digits.

Encoding

Binary Layout
0
0:5
FRT
6:10
FRA
11:15
FRB
16:20
RMC
21:30
Rc
31
 
Format Z23-form
Opcode 0xEC000046
Extension Decimal Floating-Point

Operands

  • FRT
    Target Floating-Point Register
  • FRA
    Source Floating-Point Register containing the reference significance
  • FRB
    Source Floating-Point Register containing the value to be rounded
  • RMC
    Rounding Mode Control
  • k
    Number of significant digits

Example

drrnd f1, f2, f3, 0

Registers Altered

FPSCR, (FPRF, FR, FI, FX, XX), VXSNAN, VXCVI, CR0

Related

More in Decimal Floating-Point

Reference

View in PowerISA v3.1C Specification ↗ OPF Power ISA v3.1C

Description

Rounds a decimal floating-point value in FRB to the number of significant digits specified in FRA, using the rounding mode in RMC, and stores the result in FRT. This instruction is part of the Decimal Floating-Point category. The Rc bit controls whether the condition register CR1 is updated with FPCC and exception flags.

Operation

k ← DecimalSignificance(FRA)
FPR(FRT) ← RoundDecimal(FRB, k, RMC)
if Rc = 1 then CR1 ← FPCC || FPSCR[OX,UX,ZX,XX]

Programming Note

DFP Reround can be used to adjust a DFP value to have no more than a specified number of significant digits. The result is right-justified and rounded as specified by RMC.