xxgenpcvhm

VSX Generate PCV from Halfword Mask

xxgenpcvhm XT, XB, IMM

Generates a permute control vector (PCV) based on the halfword mask in VSR[VRB+32].

Details

The instruction generates a permute control vector (PCV) based on the halfword mask in VSR[VRB+32] and stores it in VSR[XT]. The operation depends on the value of IMM.

Pseudocode Operation

if MSR.VSX=0 then VSX_Unavailable()

if IMM=0b00000 then do  // Big-Endian expansion
    j ←0
    do i = 0 to 7
        if VSR[VRB+32].hword[i].bit[0]=1 then do
            VSR[XT].hword[i].byte[0] ←2×j + 0x00
            VSR[XT].hword[i].byte[1] ←2×j + 0x01
            j ←j + 1
        end else do
            VSR[XT].hword[i].byte[0] ←2×i + 0x10
            VSR[XT].hword[i].byte[1] ←2×i + 0x11
        end
    end
end else if IMM=0b00001 then do  // Big-Endian compression
    j ←0
    do i = 0 to 7
        if VSR[VRB+32].hword[i].bit[0]=1 then do
            VSR[XT].hword[j].byte[0] ←2×i + 0x00
            VSR[XT].hword[j].byte[1] ←2×i + 0x01
            j ←j + 1
        end
    end
    do i = j to 7
        VSR[XT].hword[i] ←0xUUUU
    end
end else if IMM=0b00010 then do  // Little-Endian expansion
    j ←0
    do i = 0 to 7
        if VSR[VRB+32].hword[7-i].bit[0]=1 then do
            VSR[XT].hword[7-i].byte[1] ←2×j + 0x00
            VSR[XT].hword[7-i].byte[0] ←2×j + 0x01
            j ←j + 1
        end else do
            VSR[XT].hword[7-i].byte[1] ←2×i + 0x10
            VSR[XT].hword[7-i].byte[0] ←2×i + 0x11
        end
    end
end else if IMM=0b00011 then do  // Little-Endian compression
    j ←0
    do i = 0 to 7
        if VSR[VRB+32].hword[7-i].bit[0]=1 then do
            VSR[XT].hword[7-j].byte[1] ←2×i + 0x00
            VSR[XT].hword[7-j].byte[0] ←2×i + 0x01
            j ←j + 1
        end
    end
    do i = j to 7
        VSR[XT].hword[7-i] ←0xUUUU
    end
end

Programming Note

This instruction is used for generating permute control vectors based on a halfword mask. Ensure that the VSX facility is enabled in the MSR register to avoid an exception. The operation mode (expansion or compression) and byte order (big-endian or little-endian) are determined by the IMM field. Be cautious with alignment as it affects how the data is interpreted within the vector registers.

Example

xxgenpcvhm vs1, vs3, 1

Encoding

Binary Layout

IMM

917

Format XX2-form

Opcode 0xF0000395

Extension VSX

Registers Altered MSR

Operands

XT
Target
XB
Source
IMM
Mask
VRB
Source Vector Register