ftdiv

Float Test for Divide

ftdiv BF, FRA, FRB

Tests the double-precision floating-point operand in register FRB and sets flags based on certain conditions.

Encoding

Binary Layout

0:5

6:8

9:10

FRA

11:15

FRB

16:20

128

21:30

Format X-form

Opcode 0xFC000100

Extension Floating-Point

Operands

BF
CR Field
FRA
A
FRB
B

Example

ftdiv cr0, f2, f3

Registers Altered

CR, FPSCR

Reference

View in PowerISA v3.1C Specification ↗ OPF Power ISA v3.1C

Description

This instruction tests the double-precision floating-point operand in register FRB and sets flags based on certain conditions related to its value and exponent. The CR field BF is updated accordingly.

Operation

Let e_a be the unbiased exponent of the double-precision floating-point operand in register FRA.
Let e_b be the unbiased exponent of the double-precision floating-point operand in register FRB.

fe_flag is set to 1 if any of the following conditions occur:
• The double-precision floating-point operand in register FRA is a NaN or an Infinity.
• The double-precision floating-point operand in register FRB is a Zero, a NaN, or an Infinity.
• e_b is less than or equal to -1022.
• e_b is greater than or equal to 1021.
• The double-precision floating-point operand in register FRA is not a zero and the difference, e_a - e_b, is greater than or equal to 1023.
• The double-precision floating-point operand in register FRA is not a zero and the difference, e_a - e_b, is less than or equal to -1021.
• The double-precision floating-point operand in register FRA is not a zero and e_a is less than or equal to -970.

Otherwise fe_flag is set to 0.

gf_flag is set to 1 if the following condition occurs:
• The double-precision floating-point operand in register FRB is a Zero, an Infinity, or a denormalized value.
• The double-precision floating-point operand in register FRA is an Infinity.

Otherwise fg_flag is set to 0.

If the implementation guarantees a relative error of fre[s][.] of less than or equal to 2^-14, then fl_flag is set to 1. Otherwise fl_flag is set to 0.

CR field BF is set to the value fl_flag || fg_flag || fe_flag || 0b0.

Programming Note

ftdiv and ftsqrt are provided to accelerate software emulation of divide and square root operations, by performing the requisite special case checking. Software needs only a single branch, on FE=1 (in CR[BF]), to a special case handler. FG and FL may provide further acceleration opportunities.