stxv

Store VSX Vector

stxv XS, DQ(RA)

Stores a 128-bit vector to memory (VSX aligned offset).

Encoding

Binary Layout
61
0:5
XS
6:10
RA
11:15
DQ
16:27
5
28:30
TX
31
 
Format DQ-form
Opcode 0xF4000005
Extension VSX

Operands

  • XS
    Source
  • DQ
    Offset
  • RA
    Base
  • disp
    Displacement value
  • VX
    VSX Register
  • RB
    Index General Purpose Register
  • VS32
    Source VSX Register

Example

stxv vs1, 0(r4)

Registers Altered

MSR

Related

More in VSX

Reference

View in PowerISA v3.1C Specification ↗ OPF Power ISA v3.1C

Description

For stxv, the contents of VSR[XS] are stored into memory at the effective address (EA), which is the sum of the contents of GPR[RA] and the value DQ sign-extended to 64 bits. If RA=0, EA is set to 0.

Operation

if 'stxv' & SX=0 & MSR.VSX=0 then VSX_Unavailable()
if 'stxv' & SX=1 & MSR.VEC=0 then Vector_Unavailable()
EA ← (RA|0) + EXTS64(DQ||0b0000)
MEM(EA,16) ← VSR[32×SX+S]

Programming Note

The stxv instruction stores a VSX vector from the VSR register to memory. Ensure that the VSX or Vector facility is enabled in the MSR register based on the SX field value. The effective address (EA) is calculated by adding the contents of GPR[RA] and the sign-extended DQ value. If RA is 0, EA defaults to 0. This instruction operates at user privilege level unless otherwise specified.