xscmpoqp

VSX Scalar Compare Ordered Quad-Precision

xscmpoqp BF,VRA,VRB

Compares two quad-precision floating-point values and updates the condition register.

Encoding

Binary Layout

0:5

6:8

9:10

FRA

11:15

FRB

16:20

132

21:30

Format X-form

Opcode 0xFC000108

Extension VSX

Operands

BF
Condition Register Field
VRA
Vector Register A
VRB
Vector Register B
VRT
Target Vector Register

Example

xscmpoqp cr0, v2, v3

Registers Altered

CR, FPSCR, VXVC

Reference

View in PowerISA v3.1C Specification ↗ OPF Power ISA v3.1C

Description

The instruction compares the contents of VSR[VRA+32] (src1) and VSR[VRB+32] (src2) represented in quad-precision format. The comparison results are stored in the CR field BF and FPSCR fields FL, FG, FE, and FU.

Operation

if MSR.VSX=0 then VSX_Unavailable()
reset_xflags()
src1 ←bfp_CONVERT_FROM_BFP128(VSR[VRA+32])
src2 ←bfp_CONVERT_FROM_BFP128(VSR[VRB+32])
if src1.class.SNaN=1 | src2.class.SNaN=1 then do
    vxsnan_flag ←0b1
    if FPSCR.VE=0 then vxvc_flag ←0b1
end else
    vxvc_flag ←src1.class.QNaN | src2.class.QNaN
if vxsnan_flag=1 then SetFX(FPSCR.VXSNAN)
if vxvc_flag=1   then SetFX(FPSCR.VXVC)
CR.bit[4×BF+32] ←FPSCR.FL ←src1 < src2
CR.bit[4×BF+33] ←FPSCR.FG ←src1 > src2
CR.bit[4×BF+34] ←FPSCR.FE ←src1 = src2
CR.bit[4×BF+35] ←FPSCR.FU ←src1.class.SNaN | src1.class.QNaN | src2.class.SNaN | src2.class.QNaN

Programming Note

This instruction is used for comparing two quad-precision floating-point numbers. Ensure that the VSX (Vector Scalar Extensions) are enabled in the MSR register to avoid an exception. Be cautious with NaN values, as they can trigger exceptions and set specific flags in FPSCR. The comparison results update both the CR field and FPSCR fields, so always check these registers after execution for proper handling of unordered comparisons or exceptions.