vsum4sbs

Vector Sum-across Partial (1/4) Signed Byte Saturate

vsum4sbs vD, vA, vB

Adds the contents of four signed byte elements from two vector registers and saturates the result.

Encoding

Binary Layout

0:5

6:10

11:15

16:20

1888

21:31

Format VA-form

Opcode 0x10000708

Extension VMX (AltiVec)

Operands

vD
Target
vA
Src A
vB
Accumulator
VRT
Target Vector Register
VRA
Source Vector Register
VRB
Source Vector Register

Example

vsum4sbs vd, va, vb

Registers Altered

VSCR.SAT

Reference

View in PowerISA v3.1C Specification ↗ OPF Power ISA v3.1C

Description

For vsum4sbs, the sum of the signed integer values in the four byte elements contained in word element i of VSR[VRA+32] is added to the signed integer value in word element i of VSR[VRB+32]. If the intermediate result is greater than 2^31-1 or less than -2^31, the result saturates and SAT is set to 1.

Operation

if MSR.VEC=0 then
    Vector_Unavailable()
do i = 0 to 3
    temp ←EXTS(VSR[VRB+32].word[i])
    do j = 0 to 3
        temp ←temp + EXTS(VSR[VRA+32].word[i].byte[j])
    end
    VSR[VRT+32].word[i] ←si32_CLAMP(temp)
    VSCR.SAT ←sat_flag
end

Programming Note

vsum4sbs is useful for accumulating sums of byte elements within words, with saturation handling. Ensure vectors are properly aligned and check VSCR.SAT after execution to handle overflow cases. This instruction operates at the user privilege level.