lharx

Load Halfword And Reserve Indexed

lharx RT, RA, RB

Atomic Load Halfword.

Encoding

Binary Layout

31

0:5

RT

6:10

RA

11:15

RB

16:20

116

21:30

0

31

 

Format X-form

Opcode 0x7C0000E8

Extension Base

Operands

• RT
  Target
• RA
  Base
• RB
  Index

Example

lharx r3, r4, r5

Related

More in Base

Reference

View in PowerISA v3.1C Specification ↗ OPF Power ISA v3.1C

Description

Load the halfword at the effective address into the low 16 bits of RT, sign-extending to 32 bits in 32-bit mode or 64 bits in 64-bit mode, and reserve the addressed halfword for atomic update. Sets the reservation granule; any store to the reserved address by any processor will clear the reservation. This instruction requires that RA or 0 is added to RB to form the effective address.

Operation

EA ← (RA | 0) + RB
RT ← EXTS(MEM(EA, 2), 16)
ReserveWord(EA)

Programming Note

Places a reservation on the cache line containing the effective address. The subsequent store-conditional (stwcx./stdcx. etc.) will fail if the reservation has been lost due to an intervening store from any processor or an exception. Always check the EQ bit in CR0 after the store-conditional.