lharx

Load Halfword And Reserve Indexed

lharx RT, RA, RB

Atomic Load Halfword.

Details

The lharx instruction loads a halfword from the memory location specified by the effective address formed by adding an index register to a base register. It also reserves the memory location for subsequent conditional store operations, ensuring atomicity.

Pseudocode Operation

r3 <- Memory[r4+r5]  // atomic load-reserve

Programming Note

Places a reservation on the cache line containing the effective address. The subsequent store-conditional (stwcx./stdcx. etc.) will fail if the reservation has been lost due to an intervening store from any processor or an exception. Always check the EQ bit in CR0 after the store-conditional.

Example

lharx r3, r4, r5

Encoding

Binary Layout
31
0
RT
6
RA
11
RB
16
116
21
0
31
 
Format X-form
Opcode 0x7C000074
Extension Base

Operands

  • RT
    Target
  • RA
    Base
  • RB
    Index