lharx

Load Halfword And Reserve Indexed

lharx RT, RA, RB

Atomic Load Halfword.

Details

Load the halfword at the effective address into the low 16 bits of RT, sign-extending to 32 bits in 32-bit mode or 64 bits in 64-bit mode, and reserve the addressed halfword for atomic update. Sets the reservation granule; any store to the reserved address by any processor will clear the reservation. This instruction requires that RA or 0 is added to RB to form the effective address.

Pseudocode Operation

EA ← (RA | 0) + RB
RT ← EXTS(MEM(EA, 2), 16)
ReserveWord(EA)

Programming Note

Places a reservation on the cache line containing the effective address. The subsequent store-conditional (stwcx./stdcx. etc.) will fail if the reservation has been lost due to an intervening store from any processor or an exception. Always check the EQ bit in CR0 after the store-conditional.

Example

lharx r3, r4, r5

Encoding

Binary Layout
31
0
RT
6
RA
11
RB
16
116
21
0
31
 
Format X-form
Opcode 0x7C0000E8
Extension Base

Operands

  • RT
    Target
  • RA
    Base
  • RB
    Index