vcipherlast

Vector Cipher Last

vcipherlast vD, vA, vB

Performs the final round of AES encryption (SubBytes, ShiftRows, AddRoundKey). No MixColumns.

Encoding

Binary Layout

4

0:5

vD

6:10

vA

11:15

vB

16:20

1289

21:31

 

Format VX-form

Opcode 0x10000509

Extension Vector Crypto

Operands

• vD
  Target
• vA
  State
• vB
  Round Key

Example

vcipherlast vd, va, vb

Registers Altered

MSR

Related

More in Vector Crypto

Reference

View in PowerISA v3.1C Specification ↗ OPF Power ISA v3.1C

Description

Perform the final round of AES encryption on 128-bit blocks. Applies SubBytes, ShiftRows, and AddRoundKey transformations (but not MixColumns, which is done in prior rounds). Operates on one or more 128-bit AES blocks. No status flags are affected.

Operation

vD ← AES_SubBytes(vA)
vD ← AES_ShiftRows(vD)
vD ← AES_AddRoundKey(vD, vB)

Programming Note

The vcipherlast instruction is used to perform the final round of AES encryption on a vector of data. Ensure that the Vector Facility (MSR.VEC) is enabled before using this instruction; otherwise, a Vector_Unavailable exception will be raised. This instruction processes each 32-bit word of the input data with the corresponding round key from the VRA register to produce the encrypted output in the VRT register.