xvf16ger2

VSX Vector Float16 GER (Rank-2 Update)

xvf16ger2 AT, XA, XB

Performs a vector floating-point general element-wise rank-2 update operation.

Encoding

Binary Layout

59

0:5

AT

6:8

//

9:10

A

11:15

B

16:20

19

21:28

AX

29

BX

30

/

31

 

Format XX3-form

Opcode 0xEC000098

Extension MMA

Operands

• AT
  Accumulator
• XA
  Src A (FP16)
• XB
  Src B (FP16)

Example

xvf16ger2 acc0, vs2, vs3

Related

More in MMA

Reference

View in PowerISA v3.1C Specification ↗ OPF Power ISA v3.1C

Description

Performs a rank-2 outer product of two FP16 (half-precision floating-point) vectors, accumulating the result into the 512-bit accumulator AT. Each element of XA is multiplied by each element of XB, and products are summed across appropriate lanes. This MMA instruction requires floating-point support and does not modify condition registers or status fields.

Operation

for i = 0 to 31 do
  for j = 0 to 31 do
    ACC[AT][result_lane] ← ACC[AT][result_lane] + (fp16)XA[16×i:16×i+15] × (fp16)XB[16×j:16×j+15]
  end for
end for

Programming Note

The xvf16ger2 instruction is useful for performing matrix operations in VSX registers, specifically for rank-2 update accumulations. Ensure that the input matrices are correctly aligned and that the destination accumulator register is properly initialized to avoid incorrect results. This instruction operates at a high privilege level and may raise exceptions if the operands are not valid bfloat16 values.