vextsh2w

Vector Extend Sign Halfword To Word

vextsh2w vD, vB

Sign-extends halfwords to words.

Details

Sign-extends each of four 16-bit halfwords in the source vector to 32-bit words, filling the upper bits with the sign bit, and stores the result in the destination vector. The instruction operates on the four halfwords in the lower 64 bits of the source. No condition flags are affected; this is a VMX/AltiVec instruction.

Pseudocode Operation

vD[0:31] ← (vB[0] replicated to 16 bits) || vB[0:15]
vD[32:63] ← (vB[16] replicated to 16 bits) || vB[16:31]
vD[64:95] ← (vB[32] replicated to 16 bits) || vB[32:47]
vD[96:127] ← (vB[48] replicated to 16 bits) || vB[48:63]

Programming Note

This instruction is used to sign-extend the upper half of each word in a vector register. Ensure that the Vector Facility (MSR.VEC) is enabled before using this instruction; otherwise, it will raise an exception. The operation processes four 32-bit words per vector register, and there are no specific alignment requirements for the data.

Example

vextsh2w vd, vb

Encoding

Binary Layout
4
0
vD
6
0
11
vB
16
1606
21
 
Format VX-form
Opcode 0x10110602
Extension VMX (AltiVec)
Registers Altered MSR

Operands

  • vD
    Target
  • vB
    Source