vextsh2w

Vector Extend Sign Halfword To Word

vextsh2w vD, vB

Sign-extends halfwords to words.

Details

The Vector Extend Sign Halfword To Word instruction sign-extends the signed integer in bits 16:31 of each word element from the source vector register to a full 32-bit word and places the result into the corresponding word element of the destination vector register.

Pseudocode Operation

if MSR.VEC=0 then Vector_Unavailable()
do i = 0 to 3
   src ←VSR[VRB+32].word[i].bit[16:31]
   VSR[VRT+32].word[i] ←EXTS32(src)
end

Programming Note

This instruction is used to sign-extend the upper half of each word in a vector register. Ensure that the Vector Facility (MSR.VEC) is enabled before using this instruction; otherwise, it will raise an exception. The operation processes four 32-bit words per vector register, and there are no specific alignment requirements for the data.

Example

vextsh2w vd, vb

Encoding

Binary Layout
4
0
vD
6
0
11
vB
16
1606
21
 
Format VX-form
Opcode 0x10000646
Extension VMX (AltiVec)
Registers Altered MSR

Operands

  • vD
    Target
  • vB
    Source