xmsubasp

VSX Scalar Multiply-Subtract Type-A Single-Precision

xmsubasp XT,XA,XB

Performs a multiply-subtract operation on single-precision floating-point values.

Details

For xmsubasp, the double-precision floating-point value in doubleword element 0 of VSR[XA] is multiplied by the double-precision floating-point value in doubleword element 0 of VSR[XB], and the result is subtracted from the double-precision floating-point value in doubleword element 0 of VSR[XT]. The result is then rounded to single-precision format and placed into doubleword element 0 of VSR[XT] in double-precision format.

Pseudocode Operation

if MSR.VSX=0 then VSX_Unavailable()
reset_xflags()
src1 ←bfp_CONVERT_FROM_BFP64(VSR[32×AX+A].dword[0])
src2 ←bfp_CONVERT_FROM_BFP64(VSR[32×TX+T].dword[0])
src3 ←bfp_CONVERT_FROM_BFP64(VSR[32×BX+B].dword[0])
v ←bfp_MULTIPLY_ADD(src1, src3, bfp_NEGATE(src2))
rnd ←bfp_ROUND_TO_BFP32(FPSCR.RN, v)
result32 ←bfp32_CONVERT_FROM_BFP(rnd)
result64 ←bfp64_CONVERT_FROM_BFP(rnd)
if vxsnan_flag=1 then SetFX(FPSCR.VXSNAN)
if vximz_flag=1 then SetFX(FPSCR.VXIMZ)
if vxisi_flag=1 then SetFX(FPSCR.VXISI)
if ox_flag=1 then SetFX(FPSCR.OX)
if ux_flag=1 then SetFX(FPSCR.UX)
if xx_flag=1 then SetFX(FPSCR.XX)
vx_flag  ←vxsnan_flag | vximz_flag | vxisi_flag
vex_flag ←FPSCR.VE & vx_flag
if vex_flag=0 then do
    VSR[32×TX+T].dword[0] ←result64
    VSR[32×TX+T].dword[1] ←0x0000_0000_0000_0000
    FPSCR.FPRF ←fprf_CLASS_BFP32(result32)
    FPSCR.FR  ←inc_flag
    FPSCR.FI  ←xx_flag
else do
    FPSCR.FR  ←0b0
    FPSCR.FI  ←0b0

Programming Note

This instruction is commonly used for performing complex floating-point arithmetic operations in single-precision format while maintaining double-precision intermediate results. Ensure that the VSX (Vector Scalar Extensions) are enabled, as attempting to use this instruction without them will result in an unavailable exception. Be cautious of rounding modes and exceptions; check the FPSCR register for flags indicating overflow, underflow, or invalid operations. The instruction requires proper alignment of input values in VSR registers, specifically targeting doubleword elements.

Example

xmsubasp vs1, vs2, vs3

Encoding

Binary Layout
18
0
T
6
A
11
B
16
AX
21
BX
26
TX
31
 
Format XX3-form
Opcode 0xF0000088
Extension VSX
Registers Altered FPSCR, VSR[XT], FPRF

Operands

  • XT
    Target Vector-Scalar Register
  • XA
    Source Vector-Scalar Register
  • XB
    Source Vector-Scalar Register