stbci

Store Byte Caching Inhibited

stbci RS, RA, RB

Stores a byte bypassing the cache.

Details

Stores the low-order byte from RS to memory at address (RA + RB) with caching inhibited. This instruction bypasses the cache hierarchy and is typically used for memory-mapped I/O operations. No condition registers are affected.

Pseudocode Operation

EA ← (RA) + (RB); [EA] ← (RS)[56:63]

Example

stbci r3, r4, r5

Encoding

Binary Layout
31
0
RS
6
RA
11
RB
16
982
21
/
31
 
Format X-form
Opcode 0x7C0007AE
Extension Base

Operands

  • RS
    Source
  • RA
    Base
  • RB
    Index