stbci

Store Byte Caching Inhibited

stbci RS, RA, RB

Stores a byte bypassing the cache.

Details

The Store Byte Caching Inhibited instruction stores a byte bypassing the cache.

Pseudocode Operation

Memory[address] <- r3

Example

stbci r3, r4, r5

Encoding

Binary Layout

31

0

RS

6

RA

11

RB

16

982

21

/

31

Format X-form

Opcode 0x7C0007AE

Extension Base

Operands

RS
Source
RA
Base
RB
Index