stbci

Store Byte Caching Inhibited

stbci RS, RA, RB

Stores a byte bypassing the cache.

Encoding

Binary Layout

31

0:5

RS

6:10

RA

11:15

RB

16:20

982

21:30

/

31

 

Format X-form

Opcode 0x7C0007AE

Extension Base

Operands

• RS
  Source
• RA
  Base
• RB
  Index

Example

stbci r3, r4, r5

Related

More in Base

Reference

View in PowerISA v3.1C Specification ↗ OPF Power ISA v3.1C

Description

Stores the low-order byte from RS to memory at address (RA + RB) with caching inhibited. This instruction bypasses the cache hierarchy and is typically used for memory-mapped I/O operations. No condition registers are affected.

Operation

EA ← (RA) + (RB); [EA] ← (RS)[56:63]