stswx

Store String Word Indexed

stswx RT, RA, RB

Stores N bytes to memory (N in XER).

Encoding

Binary Layout

31

0:5

RT

6:10

RA

11:15

RB

16:20

661

21:30

/

31

 

Format X-form

Opcode 0x7C00052A

Extension Base

Operands

• RT
  Start Reg
• RA
  Base
• RB
  Index

Example

stswx r3, r4, r5

Registers Altered

XER

Related

More in Base

Reference

View in PowerISA v3.1C Specification ↗ OPF Power ISA v3.1C

Description

Stores a variable number of bytes from a sequence of GPRs starting at RT to memory, where the byte count is stored in XER[25:31]. Bytes are stored from consecutive 32-bit words to address RA|0 (or RA + RB if RA is non-zero). This is a Base category instruction that does not affect condition registers.

Operation

N ← XER[25:31]
addr ← (RA == 0) ? 0 : RA + RB
reg ← RT
for i ← 0 to N-1
  byte_offset ← i mod 4
  if byte_offset == 0 and i > 0 then
    reg ← (reg + 1) mod 32
  [addr + i] ← reg[8*byte_offset:8*byte_offset+7]

Programming Note

String instructions are not pipelined on most implementations and can be very slow for large counts. Consider using byte loops or vector instructions for performance-critical paths. NB: these instructions are optional in Power ISA 3.0+ and may trap on some implementations.