stswx

Store String Word Indexed

stswx RT, RA, RB

Stores N bytes to memory (N in XER).

Details

The stswx instruction stores a string of words into memory, starting at the effective address formed by adding the contents of register RA and RB. The number of bytes to store is determined by the XER57:63 field. If RA or RB is in the range of registers being stored, including RT, the instruction form is invalid.

Pseudocode Operation

if RA = 0 then b ← 0
else           b ← (RA)
EA ← b + (RB)
n ← XER57:63
r ← RT - 1
i ← 32
do while n > 0
   if i = 32 then
      r ← r + 1 (mod 32)
      GPR(r) ← 0
   GPR(r)i:i+7 ← MEM(EA, 1)
   i ← i + 8
   if i = 64 then i ← 32
   EA ← EA + 1
   n ← n - 1
if n > 0, n consecutive bytes starting at EA are stored into GPRs RT through RT+nr-1. Data are stored from the low-order four bytes of each GPR. If RA or RB is in the range of registers to be loaded, including RT, the instruction form is invalid.

Programming Note

String instructions are not pipelined on most implementations and can be very slow for large counts. Consider using byte loops or vector instructions for performance-critical paths. NB: these instructions are optional in Power ISA 3.0+ and may trap on some implementations.

Example

stswx r3, r4, r5

Encoding

Binary Layout
31
0
RT
6
RA
11
RB
16
661
21
/
31
 
Format X-form
Opcode 0x7C000525
Extension Base
Registers Altered XER

Operands

  • RT
    Start Reg
  • RA
    Base
  • RB
    Index