vmrghh

Vector Merge High Halfword

vmrghh vD, vA, vB

Merges the high halfwords of two vector registers into a target vector register.

Encoding

Binary Layout

0:5

6:10

11:15

16:20

21:31

Format VX-form

Opcode 0x1000004C

Extension VMX (AltiVec)

Operands

vD
Target
vA
Src A
vB
Src B
VRT
Target Vector Register
VRA
Source Vector Register
VRB
Source Vector Register

Example

vmrghh vd, va, vb

Registers Altered

MSR

Reference

View in PowerISA v3.1C Specification ↗ OPF Power ISA v3.1C

Description

For vmrghh, the contents of halfword elements 0 to 3 of VSR[VRA+32] are placed into halfword elements 0 to 7 of VSR[VRT+32], and the contents of halfword elements 0 to 3 of VSR[VRB+32] are placed into halfword elements 1 to 8 of VSR[VRT+32].

Operation

if MSR.VEC=0 then
    Vector_Unavailable()
do i = 0 to 3
    VSR[VRT+32].word[i].hword[0] ← VSR[VRA+32].hword[i]
    VSR[VRT+32].word[i].hword[1] ← VSR[VRB+32].hword[i]

Programming Note

The vmrghh instruction is used to merge the high halfwords from two vector registers into a single destination register. Ensure that the Vector Facility (MSR.VEC) is enabled before using this instruction; otherwise, it will raise an exception. This operation is useful for combining data from two sources into one vector, but be cautious of alignment issues if the data elements are not properly aligned to halfword boundaries.