vmrghw

Vector Merge High Word

vmrghw vD, vA, vB

Merges the high words of two vector registers into a target vector register.

Encoding

Binary Layout
O
0
O
6
O
11
O
16
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
 
Format VX-form
Opcode 0x1000008C
Extension VMX (AltiVec)

Operands

  • vD
    Target
  • vA
    Src A
  • vB
    Src B
  • VRT
    Target Vector Register
  • VRA
    Source Vector Register
  • VRB
    Source Vector Register
  • VT
    Target Vector Register
  • VS30
    Source Vector Register
  • VS31
    Source Vector Register

Example

vmrghw vd, va, vb

Registers Altered

MSR

Related

More in VMX (AltiVec)

Reference

View in PowerISA v3.1C Specification ↗ OPF Power ISA v3.1C

Description

The contents of word element 0 of VSR[VRA+32] are placed into word element 0 of VSR[VRT+32]. The contents of word element 0 of VSR[VRB+32] are placed into word element 1 of VSR[VRT+32]. The contents of word element 1 of VSR[VRA+32] are placed into word element 2 of VSR[VRT+32]. The contents of word element 1 of VSR[VRB+32] are placed into word element 3 of VSR[VRT+32].

Operation

if MSR.VEC=0 then
    Vector_Unavailable()
else
    VSR[VRT+32].word[0] ← VSR[VRA+32].word[0]
    VSR[VRT+32].word[1] ← VSR[VRB+32].word[0]
    VSR[VRT+32].word[2] ← VSR[VRA+32].word[1]
    VSR[VRT+32].word[3] ← VSR[VRB+32].word[1]

Programming Note

The vmrghw instruction is used to merge high words from two vector registers into a third. Ensure that the Vector Facility (MSR.VEC) is enabled before using this instruction; otherwise, it will raise an exception. This operation is useful for combining specific elements from different vectors into a single output vector.