vmulesh

Vector Multiply Even Signed Halfword

vmulesh vD, vA, vB

Multiplies the even-numbered halfwords of two vector registers and places the results into a destination vector register.

Encoding

Binary Layout

0:5

VRT

6:10

VRA

11:15

VRB

16:20

840

21:31

Format VX-form

Opcode 0x10000348

Extension VMX (AltiVec)

Operands

vD
Target
vA
Src A
vB
Src B
VRT
Target Vector Register
VRA
Source Vector Register
VRB
Source Vector Register

Example

vmulesh vd, va, vb

Registers Altered

MSR

Reference

View in PowerISA v3.1C Specification ↗ OPF Power ISA v3.1C

Description

For vmulesh, the signed integer value in each even-numbered halfword element of VSR[VRA+32] is multiplied by the corresponding signed integer value in each even-numbered halfword element of VSR[VRB+32]. The 32-bit product is placed into each word element of VSR[VRT+32].

Operation

if MSR.VEC=0 then
    Vector_Unavailable()
do i = 0 to 3
    src1 ←EXTS(VSR[VRA+32].hword[2×i])
    src2 ←EXTS(VSR[VRB+32].hword[2×i])
    VSR[VRT+32].word[i] ←CHOP32(src1 × src2)
end

Programming Note

This instruction is used for multiplying signed halfwords from two vector registers and storing the 32-bit results in another vector register. Ensure that the Vector Facility (MSR.VEC) is enabled before using this instruction; otherwise, a Vector_Unavailable exception will be raised. The operation processes even-numbered halfwords, so developers should ensure proper alignment of data within the vector registers to avoid unexpected results.