xvmaddadp

VSX Vector Multiply-Add Double-Precision

xvmaddadp XT, XA, XB

Performs a double-precision floating-point multiply-add operation on vector elements.

Encoding

Binary Layout

1000

0:5

6:10

11:15

16:20

0000

21:28

0000

Format XX3-form

Opcode 0xF0000308

Extension VSX

Operands

XT
Target/Addend (Accumulator)
XA
Multiplier
XB
Multiplicand

Example

xvmaddadp 0, 1, 2

// Vector FMA.

Registers Altered

FPSCR

Reference

View in PowerISA v3.1C Specification ↗ OPF Power ISA v3.1C

Description

For xvmaddadp, the double-precision floating-point operand in doubleword element i of VSR[XA] is multiplied by the double-precision floating-point operand in doubleword element i of VSR[XB], and then added to the double-precision floating-point operand in doubleword element i of VSR[XT]. The result is normalized and rounded to double precision.

Operation

if MSR.VSX=0 then VSX_Unavailable()
ex_flag ←0b0
do i = 0 to 1
    reset_xflags()
    src1 ←bfp_CONVERT_FROM_BFP64(VSR[32×AX+A].dword[i])
    src2 ←bfp_CONVERT_FROM_BFP64(VSR[32×TX+T].dword[i])
    src3 ←bfp_CONVERT_FROM_BFP64(VSR[32×BX+B].dword[i])
    v   ←bfp_MULTIPLY_ADD(src1,src3,src2)
    rnd ←bfp_ROUND_TO_BFP64(0b0,FPSCR.RN,v)
    vresult.dword[i] ←bfp64_CONVERT_FROM_BFP(rnd)
    if vxsnan_flag=1 then SetFX(FPSCR.VXSNAN)
    if vximz_flag=1 then SetFX(FPSCR.VXIMZ)
    if vxisi_flag=1 then SetFX(FPSCR.VXISI)
    if ox_flag=1 then SetFX(FPSCR.OX)
    if ux_flag=1 then SetFX(FPSCR.UX)
    if xx_flag=1 then SetFX(FPSCR.XX)
    ex_flag ←ex_flag | (FPSCR.VE & vxsnan_flag) | (FPSCR.VE & vximz_flag) | (FPSCR.VE & vxisi_flag) | (FPSCR.OE & ox_flag) | (FPSCR.UE & ux_flag) | (FPSCR.XE & xx_flag)
end
if ex_flag=0 then VSR[32×TX+T] ←result

Programming Note

This instruction is commonly used for performing vectorized floating-point operations in parallel, which can significantly speed up computations involving large datasets. Ensure that the VSX (Vector Scalar Extensions) are enabled by checking and setting the appropriate bits in the MSR register. Be cautious of potential exceptions such as NaNs or infinities, which can trigger flags in the FPSCR register. The instruction operates on double-precision floating-point numbers, so ensure proper alignment and data types to avoid undefined behavior.