xvcvsxddp

VSX Vector Convert with round Signed Doubleword to Double-Precision format

xvcvsxddp XT,XB

Converts signed doublewords from a vector register to double-precision floating-point values and rounds them.

Encoding

Binary Layout

0:5

6:10

11:15

16:31

Format XX2-form

Opcode 0xF00007E0

Extension VSX

Operands

XT
Target Vector Register
XB
Source Vector Register

Example

xvcvsxddp vs1, vs3

Registers Altered

FPSCR.FX, FPSCR.XX

Reference

View in PowerISA v3.1C Specification ↗ OPF Power ISA v3.1C

Description

The instruction converts each signed doubleword in the source vector register (VSR[XB]) to a double-precision floating-point value, rounds it according to the rounding mode specified by FPSCR.RN, and stores the result in the target vector register (VSR[XT]).

Operation

if MSR.VSX=0 then VSX_Unavailable()

ex_flag ←0b0

do i = 0 to 1
    reset_xflags()

    src ←bfp_CONVERT_FROM_SI64(VSR[32×BX+B].dword[i])
    rnd ←bfp_ROUND_TO_BFP64(0b0,FPSCR.RN,v)

    vresult.dword[i] ←bfp64_CONVERT_FROM_BFP(rnd)

    if xx_flag=1 then SetFX(FPSCR.XX)

    ex_flag ←ex_flag | (FPSCR.XE & xx_flag)
end

if ex_flag=0 then VSR[32×TX+T] ←vresult

Programming Note

This instruction is commonly used for converting signed doubleword integers to double-precision floating-point numbers in vector operations. Ensure that the VSX (Vector Scalar Extensions) are enabled by checking and setting the MSR.VSX bit. Be aware of rounding modes specified in FPSCR.RN, as they affect the precision of the conversion. Handle exceptions by checking FPSCR.XE and FPSCR.XX flags after execution.