xvtstdcdp

VSX Vector Test Data Class Double-Precision

xvtstdcdp XT,XB,DCMX

Tests each double-precision floating-point element in a vector against specified data classes and sets the corresponding elements in another vector to either all ones or all zeros based on the match.

Details

For xvtstdcdp, each double-precision floating-point value in VSR[XB] is tested against the data classes specified by DCMX. If a match is found, the corresponding element in VSR[XT] is set to 0xFFFF_FFFF_FFFF_FFFF; otherwise, it is set to 0x0000_0000_0000_0000.

Pseudocode Operation

if MSR.VSX=0 then VSX_Unavailable()

DCMX ← dc || dm || dx
XT ← 32×TX + T
do i = 0 to 1
    src ← VSR[32×BX+B].dword[i]
    sign ← src.bit[0]
    exponent ← src.bit[1:11]
    fraction ← src.bit[12:63]

    class.Infinity ← (exponent = 0x7FF) & (fraction = 0)
    class.NaN ← (exponent = 0x7FF) & (fraction ≠ 0)
    class.Zero ← (exponent = 0x000) & (fraction = 0)
    class.Denormal ← (exponent = 0x000) & (fraction ≠ 0)

    match ←
        (DCMX.bit[0] & class.NaN) |
        (DCMX.bit[1] & class.Infinity & !sign) |
        (DCMX.bit[2] & class.Infinity & sign) |
        (DCMX.bit[3] & class.Zero & !sign) |
        (DCMX.bit[4] & class.Zero & sign) |
        (DCMX.bit[5] & class.Denormal & !sign) |
        (DCMX.bit[6] & class.Denormal & sign)

    if match = 1 then
        VSR[XT].dword[i] ← 0xFFFF_FFFF_FFFF_FFFF
    else
        VSR[XT].dword[i] ← 0x0000_0000_0000_0000
end

Programming Note

This instruction is used to test each double-precision floating-point value in a vector register against specified data classes. Ensure that the VSX (Vector Scalar Extensions) are enabled by checking and setting the appropriate bit in the Machine State Register (MSR). The instruction requires proper alignment of the source and target vector registers. Be cautious with the data class mask (DCMX) as incorrect settings can lead to unexpected results. This operation is performed at the user privilege level, but it may trigger exceptions if VSX is not available or if there are issues with register access.

Example

xvtstdcdp vs1, vs3, 0

Encoding

Binary Layout
18
0
LI
6
AA
30
LK
31
 
Format XX2-form
Opcode 0xF00007A8
Extension VSX
Registers Altered None

Operands

  • XT
    Target Vector-Specific Register
  • XB
    Source Vector-Specific Register
  • DCMX
    Data Class Mask (concatenation of dc, dm, and dx)