vmsumubm

Vector Multiply-Sum Unsigned Byte Modulo

vmsumubm vD, vA, vB, vC

Multiplies bytes and sums adjacent results into words.

Details

Multiplies each unsigned byte in vA by the corresponding byte in vB, then sums the products of adjacent byte pairs to produce four unsigned 32-bit word results. The results are added to the four words in the accumulator vC and stored in vD. This is a VMX (AltiVec) instruction that does not affect condition or status flags.

Pseudocode Operation

vD[0:31] ← (vA[0:7] × vB[0:7]) + (vA[8:15] × vB[8:15]) + vC[0:31]
vD[32:63] ← (vA[16:23] × vB[16:23]) + (vA[24:31] × vB[24:31]) + vC[32:63]
vD[64:95] ← (vA[32:39] × vB[32:39]) + (vA[40:47] × vB[40:47]) + vC[64:95]
vD[96:127] ← (vA[48:55] × vB[48:55]) + (vA[56:63] × vB[56:63]) + vC[96:127]

Programming Note

This instruction is commonly used for performing efficient vectorized operations on unsigned byte data. Ensure that the Vector Facility (MSR.VEC) is enabled before using this instruction; otherwise, a Vector_Unavailable exception will be raised. The operation processes 8 bytes per iteration, multiplying corresponding elements and adding to the third source vector's word element, storing the result in the destination vector. Be cautious of overflow as only the low-order 16 bits are stored.

Example

vmsumubm vd, va, vb, vc

Encoding

Binary Layout
4
0
vD
6
vA
11
vB
16
vC
21
36
26
 
Format VA-form
Opcode 0x10000024
Extension VMX (AltiVec)
Registers Altered MSR

Operands

  • vD
    Target
  • vA
    Src A
  • vB
    Src B
  • vC
    Accumulator