vadduhs

Vector Add Unsigned Halfword Saturate

vadduhs vD, vA, vB

Adds the contents of two vector registers and saturates the result.

Details

The vadduhs instruction performs an unsigned addition of each pair of halfwords from the source registers VRA and VRB, saturating the result to fit within a halfword. The results are stored in the destination register VRT.

Pseudocode Operation

if MSR.VEC=0 then Vector_Unavailable()
do i = 0 to 7
   src1 ←EXTZ(VSR[VRA+32].hword[i])
   src2 ←EXTZ(VSR[VRB+32].hword[i])
   VSR[VRT+32].hword[i] ←ui16_CLAMP(src1 + src2)
end

Programming Note

The vadduhs instruction is commonly used for adding pairs of unsigned halfwords with saturation, which prevents overflow by clamping results to the maximum representable value. Ensure that the Vector Facility (MSR.VEC) is enabled before using this instruction; otherwise, a Vector_Unavailable exception will be raised. The operation processes 8 halfword elements in parallel, and both source registers must be properly aligned for optimal performance.

Example

vadduhs vd, va, vb

Encoding

Binary Layout
4
0
vD
6
vA
11
vB
16
576
21
 
Format VX-form
Opcode 0x10000240
Extension VMX (AltiVec)
Registers Altered MSR

Operands

  • vD
    Target
  • vA
    Src A
  • vB
    Src B
  • VRT
    Target Vector Register
  • VRA
    Source Vector Register
  • VRB
    Source Vector Register