vadduhs

Vector Add Unsigned Halfword Saturate

vadduhs vD, vA, vB

Adds the contents of two vector registers and saturates the result.

Encoding

Binary Layout

0:5

6:10

11:15

16:20

576

21:31

Format VX-form

Opcode 0x10000240

Extension VMX (AltiVec)

Operands

vD
Target
vA
Src A
vB
Src B
VRT
Target Vector Register
VRA
Source Vector Register
VRB
Source Vector Register

Example

vadduhs vd, va, vb

Registers Altered

MSR

Reference

View in PowerISA v3.1C Specification ↗ OPF Power ISA v3.1C

Description

Adds each of eight unsigned 16-bit halfwords in vA to the corresponding halfword in vB, with saturation at the unsigned range [0, 65535]. Any result exceeding 65535 is clamped to 65535; no status flags are affected.

Operation

for i in 0 to 7 do
  sum ← vA[i*16:(i+1)*16-1] + vB[i*16:(i+1)*16-1]
  if sum > 65535 then
    vD[i*16:(i+1)*16-1] ← 65535
  else
    vD[i*16:(i+1)*16-1] ← sum

Programming Note

The vadduhs instruction is commonly used for adding pairs of unsigned halfwords with saturation, which prevents overflow by clamping results to the maximum representable value. Ensure that the Vector Facility (MSR.VEC) is enabled before using this instruction; otherwise, a Vector_Unavailable exception will be raised. The operation processes 8 halfword elements in parallel, and both source registers must be properly aligned for optimal performance.